freebsd-ports/cad/Makefile

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Makefile
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# $FreeBSD$
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#
COMMENT = CAD tools
SUBDIR += admesh
SUBDIR += adms
SUBDIR += alliance
SUBDIR += astk-client
SUBDIR += astk-serveur
SUBDIR += atlc
SUBDIR += basicdsp
SUBDIR += brlcad
SUBDIR += calculix
SUBDIR += cascade
SUBDIR += chipmunk
SUBDIR += chipvault
SUBDIR += cider
SUBDIR += dinotrace
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SUBDIR += dxf2fig
SUBDIR += electric
SUBDIR += electric-ng
SUBDIR += feappv
SUBDIR += fidocadj
SUBDIR += findhier
SUBDIR += freehdl
SUBDIR += gdsreader
SUBDIR += gdt
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SUBDIR += geda
SUBDIR += geda-docs
SUBDIR += geda-examples
SUBDIR += geda-gattrib
SUBDIR += geda-gschem
SUBDIR += geda-netlist
SUBDIR += geda-symbols
SUBDIR += geda-symcheck
SUBDIR += geda-utils
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SUBDIR += gerbv
SUBDIR += gmsh
SUBDIR += gmsh-occ
SUBDIR += gnucap
SUBDIR += gplcver
SUBDIR += gspiceui
SUBDIR += gtkwave
SUBDIR += gwave
SUBDIR += impact
SUBDIR += irsim
SUBDIR += iverilog
SUBDIR += jspice3
SUBDIR += kicad
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SUBDIR += kicad-devel
SUBDIR += kicad-library
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SUBDIR += klayout
SUBDIR += layouteditor
SUBDIR += ldraw
SUBDIR += leocad
SUBDIR += libgeda
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SUBDIR += librecad
SUBDIR += linux-eagle5
SUBDIR += logisim
SUBDIR += magic
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SUBDIR += mars
SUBDIR += meshdev
SUBDIR += meshlab
SUBDIR += netgen
SUBDIR += ngspice_rework
SUBDIR += opencascade
SUBDIR += opencascade-tutorial
SUBDIR += openscad
SUBDIR += openvsp
SUBDIR += p5-GDS2
SUBDIR += p5-Verilog-Perl
SUBDIR += pcb
SUBDIR += pdnmesh
SUBDIR += pythoncad
SUBDIR += qcad
SUBDIR += qcad-partslib
SUBDIR += qelectrotech
SUBDIR += qfsm
SUBDIR += qmls
SUBDIR += qucs
SUBDIR += repsnapper
SUBDIR += salome
SUBDIR += salome-geom
SUBDIR += salome-gui
SUBDIR += salome-jobmanager
SUBDIR += salome-kernel
SUBDIR += salome-light
SUBDIR += salome-med
SUBDIR += salome-multipr
SUBDIR += salome-netgenplugin
SUBDIR += salome-randomizer
SUBDIR += salome-sierpinsky
SUBDIR += salome-smesh
SUBDIR += salome-visu
SUBDIR += salome-yacs
SUBDIR += sceptre
SUBDIR += scotch
SUBDIR += scv
SUBDIR += slffea
SUBDIR += spice
SUBDIR += systemc
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SUBDIR += tkgate
SUBDIR += tochnog
SUBDIR += transcalc
SUBDIR += varkon
SUBDIR += verilog-mode.el
SUBDIR += vipec
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SUBDIR += xcircuit
SUBDIR += z88
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.include <bsd.port.subdir.mk>