The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
This commit is contained in:
parent
df8c38c445
commit
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Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=234576
@ -63,6 +63,7 @@
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SUBDIR += opencascade-tutorial
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SUBDIR += oregano
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SUBDIR += p5-GDS2
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SUBDIR += p5-Verilog-Perl
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SUBDIR += pcb
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SUBDIR += pdnmesh
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SUBDIR += pythoncad
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42
cad/p5-Verilog-Perl/Makefile
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42
cad/p5-Verilog-Perl/Makefile
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# New ports collection makefile for: Verilog-Perl
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# Date created: 11 Apr 2009
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# Whom: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
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#
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# $FreeBSD$
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#
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PORTNAME= Verilog-Perl
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PORTVERSION= 3.210
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CATEGORIES= cad perl5
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MASTER_SITES= CPAN
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PKGNAMEPREFIX= p5-
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MAINTAINER= otacilio.neto@ee.ufcg.edu.br
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COMMENT= Building point for Verilog support in the Perl language
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USE_GMAKE= yes
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USE_PERL5= yes
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PERL_CONFIGURE= yes
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MAN1= vhier.1 vpassert.1 vppreproc.1 vrename.1
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MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
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Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
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Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
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Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
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Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
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Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
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Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
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post-patch:
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@${REINPLACE_CMD} -e '/EXE_FILES/ s/ vsplitmodule//' \
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${WRKSRC}/Makefile.PL
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post-build:
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cd ${WRKSRC} && make test
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test:
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make post-build
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.include <bsd.port.mk>
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3
cad/p5-Verilog-Perl/distinfo
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3
cad/p5-Verilog-Perl/distinfo
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MD5 (Verilog-Perl-3.210.tar.gz) = 4facca9c30bfdd21d03024e4272ab9c8
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SHA256 (Verilog-Perl-3.210.tar.gz) = 814bedd604017824966d98e3a81c494994d1969f8217f0349ca58f234fed8ede
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SIZE (Verilog-Perl-3.210.tar.gz) = 205250
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19
cad/p5-Verilog-Perl/pkg-descr
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19
cad/p5-Verilog-Perl/pkg-descr
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The Verilog-Perl library is a building point for Verilog support in the Perl
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language. It includes:
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* Verilog::Getopt which parses command line options similar to C++ and VCS.
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* Verilog::Language which knows the language keywords and parses numbers.
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* Verilog::Netlist which builds netlists out of Verilog files. This allows
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easy scripts to determine things such as the hierarchy of modules.
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* Verilog::Parser invokes callbacks for language tokens.
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* Verilog::Preproc preprocesses the language, and allows reading
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post-processed files right from Perl without temporary files.
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* vpassert inserts PLIish warnings and assertions for any simulator.
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* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
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* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
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cross references and makes it easy to rename signal and module names across
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multiple files. Vrename uses a simple and efficient three step process.
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First, you run vrename to create a list of signals in the design. You then
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edit this list, changing as many symbols as you wish. Vrename is then run a
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second time to apply the changes.
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WWW: http://www.veripool.org/wiki/verilog-perl
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33
cad/p5-Verilog-Perl/pkg-plist
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33
cad/p5-Verilog-Perl/pkg-plist
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bin/vhier
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bin/vpassert
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bin/vppreproc
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bin/vrename
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%%SITE_PERL%%/mach/Verilog/EditFiles.pm
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%%SITE_PERL%%/mach/Verilog/Getopt.pm
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%%SITE_PERL%%/mach/Verilog/Language.pm
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%%SITE_PERL%%/mach/Verilog/Netlist.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Cell.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/File.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Interface.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Logger.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Module.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Net.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Pin.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Port.pm
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%%SITE_PERL%%/mach/Verilog/Netlist/Subclass.pm
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%%SITE_PERL%%/mach/Verilog/Parser.pm
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%%SITE_PERL%%/mach/Verilog/Preproc.pm
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%%SITE_PERL%%/mach/Verilog/SigParser.pm
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%%SITE_PERL%%/mach/Verilog/Std.pm
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%%SITE_PERL%%/mach/Verilog/Verilog-Perl.pod
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%%SITE_PERL%%/mach/auto/Verilog/Language/.packlist
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%%SITE_PERL%%/mach/auto/Verilog/Parser/Parser.bs
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%%SITE_PERL%%/mach/auto/Verilog/Parser/Parser.so
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%%SITE_PERL%%/mach/auto/Verilog/Preproc/Preproc.bs
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%%SITE_PERL%%/mach/auto/Verilog/Preproc/Preproc.so
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@dirrm %%SITE_PERL%%/mach/auto/Verilog/Preproc
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@dirrm %%SITE_PERL%%/mach/auto/Verilog/Parser
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@dirrm %%SITE_PERL%%/mach/auto/Verilog/Language
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@dirrm %%SITE_PERL%%/mach/auto/Verilog
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@dirrm %%SITE_PERL%%/mach/Verilog/Netlist
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@dirrm %%SITE_PERL%%/mach/Verilog
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