Commit Graph

24 Commits

Author SHA1 Message Date
naddy
e93f9d0ca9 drop RCS Ids 2022-03-11 19:28:46 +00:00
sthen
b3a9eb6510 iverilog: regen plist, not done in previous update and some required files
were missed. from Alessandro De Laurenzis.
2021-05-23 19:23:52 +00:00
gnezdo
ca7b9c36eb Update lang/iverilog to 11.0
This allows it to build with CXXFLAGS=-fno-common

Added a patch from upstream to work around a case of "all-world-is-Linux"ism.

ok naddy@
2021-02-05 01:02:04 +00:00
bentley
76f13b5748 Update to iverilog-10.3. 2019-10-28 08:18:37 +00:00
sthen
3318ced016 replace simple PERMIT_PACKAGE_CDROM=Yes with PERMIT_PACKAGE=Yes 2019-07-12 20:46:54 +00:00
jca
ab7a4187d2 Enable bz2 and thus LXT file support, unbreak on ports-gcc archs
On ports-gcc archs libbz2 was detected automatically because
/usr/local/lib is in the default library path, but the build failed at
compile time because bzlib.h wasn't found in the include search paths.

Initial diff by cwen@, ok sthen@ cwen@
2019-03-01 12:47:26 +00:00
sthen
25f0e460f2 Add COMPILER lines to c++ ports which currently use the default. Adjust
some existing COMPILER lines with arch restrictions etc. In the usual
case this is now using "COMPILER = base-clang ports-gcc base-gcc" on
ports with c++ libraries in WANTLIB.

This is basically intended to be a noop on architectures using clang
as the system compiler, but help with other architectures where we
currently have many ports knocked out due to building with an unsuitable
compiler -

- some ports require c++11/newer so the GCC version in base that is used
on these archirtectures is too old.

- some ports have conflicts where an executable is built with one compiler
(e.g. gcc from base) but a library dependency is built with a different
one (e.g. gcc from ports), resulted in mixing incompatible libraries in the
same address space.

devel/gmp is intentionally skipped as it's on the path to building gcc -
the c++ library there is unused in ports (and not built by default upstream)
so intending to disable building gmpcxx in a future commit.
2018-10-24 14:27:57 +00:00
bentley
135eb6411c Update to iverilog-10.2. 2017-10-05 08:58:10 +00:00
sthen
5e964ab0df bump LIBCXX/LIBECXX/COMPILER_LIBCXX ports. 2017-07-26 22:45:14 +00:00
espie
8ac47fd9c6 use COMPILER_LIBCXX where applicable 2017-07-16 19:18:47 +00:00
sthen
bcbf44ab87 use LIBCXX 2017-04-10 11:46:18 +00:00
jasper
b52ff5a12f update to iverilog-10.1.1 2016-04-27 14:16:52 +00:00
naddy
ce859edcb4 garbage collect CONFIGURE_SHARED 2016-03-11 20:28:21 +00:00
bentley
4cd0ceb6da Update to iverilog-10.0. 2015-12-23 11:12:53 +00:00
bentley
80051cf245 Update HOMEPAGE. 2015-06-12 20:09:27 +00:00
jasper
baff6667f3 update to iverilog-0.9.7 2014-09-27 17:50:28 +00:00
bentley
71e03229ae Update to iverilog-0.9.6.
ok jasper@
2013-04-18 17:57:07 +00:00
espie
0662a4e9d6 PERMIT_* / REGRESS->TEST sweep 2013-03-11 11:20:26 +00:00
jasper
708fc01cab - update to iverilog 0.9.4 2011-06-13 19:42:25 +00:00
sthen
c13709faec update DESCR; Anthony J. Bentley 2011-03-14 08:40:20 +00:00
jasper
194263d3b2 - update iverilog to 0.9.3 2010-11-17 10:16:11 +00:00
espie
88d20077a4 new depends 2010-11-17 08:05:12 +00:00
espie
88dd25abf4 USE_GROFF=Yes 2010-10-18 19:20:41 +00:00
jasper
695182bcdf import iverilog 0.9.2
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code writen in Verilog (IEEE-1364) into
some target format. For batch simulation, the compiler can generate C++
code that is compiled and linked with a run time library (called "vvm")
then executed as a command to run the simulation. For synthesis, the
compiler generates netlists in the desired format.
2010-07-08 18:58:23 +00:00