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update DESCR; Anthony J. Bentley

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sthen 2011-03-14 08:40:20 +00:00
parent 0c592a2737
commit c13709faec
2 changed files with 9 additions and 9 deletions
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lang/iverilog/Makefile
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# $OpenBSD: Makefile,v 1.4 2010/11/17 10:16:11 jasper Exp $
# $OpenBSD: Makefile,v 1.5 2011/03/14 08:40:20 sthen Exp $
COMMENT= Verilog simulation and synthesis tool
V= 0.9.3
DISTNAME= verilog-$V
PKGNAME= iverilog-$V
REVISION= 0
CATEGORIES= lang devel
HOMEPAGE= http://www.icarus.com/eda/verilog/

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lang/iverilog/pkg/DESCR
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code writen in Verilog (IEEE-1364) into
some target format. For batch simulation, the compiler can generate C++
code that is compiled and linked with a run time library (called "vvm")
then executed as a command to run the simulation. For synthesis, the
compiler generates netlists in the desired format.
some target format. For batch simulation, the compiler can generate an
intermediate form called vvp assembly. This intermediate form is
executed by the "vvp" command. For synthesis, the compiler generates
netlists in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the year
2000. This is a fairly large and complex standard, so it will take some
time for it to get there, but that's the goal.
descriptions written to the IEEE standard IEEE Std 1364-2005. This is a
fairly large and complex standard, so it will take some time for it to
get there, but that's the goal.