import iverilog 0.9.2
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
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40
lang/iverilog/Makefile
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lang/iverilog/Makefile
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# $OpenBSD: Makefile,v 1.1.1.1 2010/07/08 18:58:23 jasper Exp $
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COMMENT= Verilog simulation and synthesis tool
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V= 0.9.2
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DISTNAME= verilog-$V
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PKGNAME= iverilog-$V
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CATEGORIES= lang devel
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HOMEPAGE= http://www.icarus.com/eda/verilog/
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# GPLv2+
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PERMIT_PACKAGE_CDROM= Yes
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PERMIT_PACKAGE_FTP= Yes
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PERMIT_DISTFILES_CDROM= Yes
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PERMIT_DISTFILES_FTP= Yes
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MASTER_SITES= ftp://ftp.icarus.com/pub/eda/verilog/v0.9/
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WANTLIB += c m readline stdc++ termcap z
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USE_GMAKE= Yes
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BUILD_DEPENDS= ::devel/bison
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YACC= bison
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CONFIGURE_STYLE= gnu
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CONFIGURE_ARGS+= ${CONFIGURE_SHARED} \
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--disable-suffix
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CFLAGS+= -fPIC
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VVP_DOCS= README.txt opcodes.txt
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DOC_DIR= ${PREFIX}/share/doc/iverilog
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post-install:
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${INSTALL_DATA_DIR} ${DOC_DIR}/{ivlpp,vvp}
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${INSTALL_DATA} ${WRKSRC}/*.txt ${DOC_DIR}
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${INSTALL_DATA} ${WRKSRC}/vvp/{README,opcodes}.txt ${DOC_DIR}/vvp/
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${INSTALL_DATA} ${WRKSRC}/ivlpp/ivlpp.txt ${DOC_DIR}/ivlpp/
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.include <bsd.port.mk>
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5
lang/iverilog/distinfo
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lang/iverilog/distinfo
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MD5 (verilog-0.9.2.tar.gz) = 47NAnwp6o4LAv7sBllX2Rw==
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RMD160 (verilog-0.9.2.tar.gz) = 2+wH3Cnfv2nbwEufO7VGdFKStjA=
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SHA1 (verilog-0.9.2.tar.gz) = zmIrV96AJX+3C3/alSmQQ87UUdQ=
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SHA256 (verilog-0.9.2.tar.gz) = MhtvMrVgjXzddFqf+OIfPi7B/rqfDj+S2L1wQtgGR8M=
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SIZE (verilog-0.9.2.tar.gz) = 1127067
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12
lang/iverilog/pkg/DESCR
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lang/iverilog/pkg/DESCR
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates
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as a compiler, compiling source code writen in Verilog (IEEE-1364) into
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some target format. For batch simulation, the compiler can generate C++
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code that is compiled and linked with a run time library (called "vvm")
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then executed as a command to run the simulation. For synthesis, the
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compiler generates netlists in the desired format.
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The compiler proper is intended to parse and elaborate design
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descriptions written to the IEEE standard IEEE Std 1364-2000. The
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standard proper is due to be release towards the middle of the year
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2000. This is a fairly large and complex standard, so it will take some
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time for it to get there, but that's the goal.
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65
lang/iverilog/pkg/PLIST
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lang/iverilog/pkg/PLIST
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@comment $OpenBSD: PLIST,v 1.1.1.1 2010/07/08 18:58:23 jasper Exp $
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@bin bin/iverilog
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bin/iverilog-vpi
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@bin bin/vvp
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include/iverilog/
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include/iverilog/_pli_types.h
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include/iverilog/acc_user.h
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include/iverilog/ivl_target.h
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include/iverilog/veriuser.h
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include/iverilog/vpi_user.h
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lib/ivl/
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@bin lib/ivl/cadpli.vpl
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lib/ivl/include/
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lib/ivl/include/constants.vams
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lib/ivl/include/disciplines.vams
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@bin lib/ivl/ivl
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@bin lib/ivl/ivlpp
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lib/ivl/null-s.conf
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lib/ivl/null.conf
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@bin lib/ivl/null.tgt
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lib/ivl/stub-s.conf
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lib/ivl/stub.conf
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@bin lib/ivl/stub.tgt
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lib/ivl/system.sft
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@bin lib/ivl/system.vpi
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lib/ivl/v2005_math.sft
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@bin lib/ivl/v2005_math.vpi
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lib/ivl/va_math.sft
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@bin lib/ivl/va_math.vpi
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lib/ivl/vhdl-s.conf
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lib/ivl/vhdl.conf
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@bin lib/ivl/vhdl.tgt
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lib/ivl/vvp-s.conf
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lib/ivl/vvp.conf
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@bin lib/ivl/vvp.tgt
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lib/libveriuser.a
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lib/libvpi.a
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@man man/man1/iverilog-vpi.1
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@man man/man1/iverilog.1
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@man man/man1/vvp.1
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share/doc/iverilog/
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@comment share/doc/iverilog/BUGS.txt
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share/doc/iverilog/QUICK_START.txt
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share/doc/iverilog/README.txt
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share/doc/iverilog/attributes.txt
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@comment share/doc/iverilog/cygwin.txt
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share/doc/iverilog/developer-quick-start.txt
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share/doc/iverilog/extensions.txt
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share/doc/iverilog/glossary.txt
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share/doc/iverilog/ieee1364-notes.txt
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share/doc/iverilog/ivl_target.txt
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share/doc/iverilog/ivlpp/
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share/doc/iverilog/ivlpp/ivlpp.txt
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share/doc/iverilog/lpm.txt
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@comment share/doc/iverilog/macosx.txt
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@comment share/doc/iverilog/mingw.txt
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share/doc/iverilog/netlist.txt
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share/doc/iverilog/swift.txt
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share/doc/iverilog/t-dll.txt
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share/doc/iverilog/va_math.txt
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share/doc/iverilog/vpi.txt
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share/doc/iverilog/vvp/
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share/doc/iverilog/vvp/README.txt
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share/doc/iverilog/vvp/opcodes.txt
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share/doc/iverilog/xilinx-hint.txt
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