695182bcdf
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
41 lines
943 B
Makefile
41 lines
943 B
Makefile
# $OpenBSD: Makefile,v 1.1.1.1 2010/07/08 18:58:23 jasper Exp $
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COMMENT= Verilog simulation and synthesis tool
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V= 0.9.2
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DISTNAME= verilog-$V
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PKGNAME= iverilog-$V
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CATEGORIES= lang devel
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HOMEPAGE= http://www.icarus.com/eda/verilog/
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# GPLv2+
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PERMIT_PACKAGE_CDROM= Yes
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PERMIT_PACKAGE_FTP= Yes
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PERMIT_DISTFILES_CDROM= Yes
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PERMIT_DISTFILES_FTP= Yes
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MASTER_SITES= ftp://ftp.icarus.com/pub/eda/verilog/v0.9/
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WANTLIB += c m readline stdc++ termcap z
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USE_GMAKE= Yes
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BUILD_DEPENDS= ::devel/bison
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YACC= bison
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CONFIGURE_STYLE= gnu
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CONFIGURE_ARGS+= ${CONFIGURE_SHARED} \
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--disable-suffix
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CFLAGS+= -fPIC
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VVP_DOCS= README.txt opcodes.txt
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DOC_DIR= ${PREFIX}/share/doc/iverilog
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post-install:
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${INSTALL_DATA_DIR} ${DOC_DIR}/{ivlpp,vvp}
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${INSTALL_DATA} ${WRKSRC}/*.txt ${DOC_DIR}
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${INSTALL_DATA} ${WRKSRC}/vvp/{README,opcodes}.txt ${DOC_DIR}/vvp/
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${INSTALL_DATA} ${WRKSRC}/ivlpp/ivlpp.txt ${DOC_DIR}/ivlpp/
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.include <bsd.port.mk>
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