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update to iverilog-10.1.1

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This commit is contained in:
jasper 2016-04-27 14:16:52 +00:00
parent 9d0d111b9d
commit b52ff5a12f
2 changed files with 6 additions and 5 deletions
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7
lang/iverilog/Makefile
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@ -1,8 +1,8 @@
# $OpenBSD: Makefile,v 1.12 2016/03/11 20:28:27 naddy Exp $
# $OpenBSD: Makefile,v 1.13 2016/04/27 14:16:52 jasper Exp $
COMMENT= Verilog simulation and synthesis tool
V= 10.0
V= 10.1.1
DISTNAME= verilog-$V
PKGNAME= iverilog-$V
CATEGORIES= lang devel
@ -12,7 +12,7 @@ HOMEPAGE= http://iverilog.icarus.com/
# GPLv2+
PERMIT_PACKAGE_CDROM= Yes
MASTER_SITES= ftp://ftp.icarus.com/pub/eda/verilog/v${V:R}/
MASTER_SITES= ftp://ftp.icarus.com/pub/eda/verilog/v10/
WANTLIB += c m pthread readline stdc++ termcap z
@ -33,4 +33,5 @@ post-install:
${INSTALL_DATA} ${WRKSRC}/*.txt ${DOC_DIR}
${INSTALL_DATA} ${WRKSRC}/vvp/{README,opcodes}.txt ${DOC_DIR}/vvp/
${INSTALL_DATA} ${WRKSRC}/ivlpp/ivlpp.txt ${DOC_DIR}/ivlpp/
.include <bsd.port.mk>

4
lang/iverilog/distinfo
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@ -1,2 +1,2 @@
SHA256 (verilog-10.0.tar.gz) = F58Jr7r7lRvqKMkAGwbti5suVBgQktSONDyyD0NrEYU=
SIZE (verilog-10.0.tar.gz) = 1683102
SHA256 (verilog-10.1.1.tar.gz) = /ap13+fFjLxHH8EnEO5Js/Mv1swFXZGBtRkMvLvWyto=
SIZE (verilog-10.1.1.tar.gz) = 1684925