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334 lines
10 KiB
HTML
334 lines
10 KiB
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<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>2.8 Baud Rate and Clocks</title>
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<link type="text/css" rel="stylesheet" href="style.css">
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</head>
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<body>
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<h1>2.8 Baud Rate and Clocks</h1>
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<blockquote> “The time has come,” the walrus said, “to talk of many things: Of baud
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rates – and clocks – and quartz.”<br>
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-- Les huit scaroles --
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</blockquote>
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One thing to consider in any kind of transmission is the speed, how fast
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or how slowly you can transmit data. I have configured <b>USART1</b> at
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<b>9600 baud</b>, keeping the other settings at default value (<b>8N1</b>),
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so how fast is that?
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<h2>A bit of theory</h2>
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Let’s interpret asynchronous serial transmission, 9600 baud, 8 bits, no
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parity, 1 stop bit.
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<ul>
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<li> Serial transmission means transmission on one wire, with each bit sent
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one after the other, usually low bit first.
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<li> Asynchronous means there is no extra wire for a clock, so transmitter
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and receiver must agree on a bit rate and a transmission pattern.
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<li> Transmission pattern, <b>8N1</b> in my case, is composed of a start bit,
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a data length (<b>8</b> bits), parity (Even, Odd or <b>N</b>one) and <b>1</b>,
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1.5 or 2 stop bits.
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<li> Because there is no common transmitted clock, the receiver
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resynchronizes based on the start bit/stop bit framing of the data. It
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samples the line at 16 times the frequency of the agreed clock to detect
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the change in the wire state.
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</ul>
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In my case, <b>8N1</b> means that, because of the framing pattern, for
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every byte of data sent, there is one extra start bit and one extra stop
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bit sent, it’s ten bits per byte of data. At 9600 bauds that means 960
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bytes per second, fast enough to transmit every characters of a 80×24
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terminal screen in two seconds.
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<h2>Baud rate accuracy</h2>
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It sounds like a pretty robust transmission scheme, sampling at 16 times
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the transmission clock isn’t call oversampling for nothing. Am I
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overdoing something here or just compensating for something I missed?
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<p>
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The thing is, I didn’t program USART1 to transmit at 9600 baud. As my
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default clock is 8MHz, I had to write in USART1 baud rate register a
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value close to 8000000/9600 or 2500/3, 833 is close enough but my actual
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transmission speed is closer to 9604, slightly faster than 9600 baud.
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<p>
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The error is small (4/10000) and the transmission works fine. Still
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common baud rates are 300, 1200, 2400, 9600, 19200, 38400, 57600, 115200.
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It would be better if my clock frequency was 6MHz or 12MHz if I
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want to work at higher baud rate.
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<h2>Clocks</h2>
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Looking at the clock tree in the datasheet can be intimidating, it’s
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definitively about several clocks.
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<p>
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<img alt="Clock Tree" src="img/28_clocktree.png">
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<p>
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The default configuration I have been using so far goes like this.
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<ul>
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<li> HSI is the output of a 8MHz High Speed Internal RC oscillator.
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<li> HSI is the default source of SYSCLK.
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<li> HCLK, the clock of AHB domain, is SYSCLK divided by HPRE a pre-scaler
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which default to 1.
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<li> The system tick clock default configuration is HCLK/8.
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<li> PCLK, the clock of APB domain, is HCLK divided by PPRE a pre-scaler
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which default to 1.
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<li> GPIO peripherals are on APB domain bus, they use PCLK.
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<li> USART1 is also on APB domain bus, but its input clock can be selected,
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PCLK is the default input.
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</ul>
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From the peripherals point of view.
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<ul>
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<li> SysTick Clock = HCLK/8 = SYSCLK/1/8 = HSI/1/8 = 8/1/8 MHz
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<li> GPIOx Clock = PCLK = HCLK/1 = SYSCLK/1/1 = HSI/1/1 = 8/1/1 MHz
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<li> USART1 Clock = PCLK = … = 8 MHz
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</ul>
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As I want to have a clock frequency different than 8 MHz as input for
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USART1, I can configure the Phase-Locked Loop (PLL) and switch SYSCLK to
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take its input from the PLL instead of HSI.
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<p>
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The PLL output frequency must be in the range 16-48 MHz. As I am looking
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for a frequency that can be divided by 3 to match most of the baud rate,
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I will use 24 MHz.
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<ul>
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<li> Select PLL input as HSI/2.
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<li> Set PLLMUL to 6.
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<li> Enable PLL and wait that it stabilizes.
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<li> Select SYSCLK input as PLL.
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<li> Wait for the switch to complete.
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</ul>
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<h2>Quartz</h2>
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I can also activate the quartz if there is one soldered on the board.
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It’s usually the case but specially for STM32F030F4 which has only 20
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pins, a quartz less design that free up two GPIO pins can be a day
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saver. Quartz value from 4 to 32 MHz are supported and most design use 8
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MHz.
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<p>
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To set a 24 MHz clock with a 8 MHz High Speed External Oscillator (HSE):
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<ul>
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<li> Enable HSE and wait that it stabilizes.
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<li> Select HSE as input for the PLL with a pre divider of 2.
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<li> Set PLLMUL to 6.
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<li> Enable PLL and wait that it stabilizes.
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<li> Select SYSCLK input as PLL.
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<li> Wait for the switch to complete.
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<li> Disable HSI.
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</ul>
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I can use different values for the pre divider and post multiplier of
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the PLL (/4, *12 or /1, *3 instead of /2, *6) but I want here to stay
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aligned with the HSI/2 input selection when HSE quartz value is 8MHz.
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<h2>Implementation</h2>
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I make a copy of <b>uplow.2.c</b> into <b>clocks.c</b> to make the changes.
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<p>
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I expand the board description part by adding <code>HSE</code>,
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<code>PLL</code> and <code>BAUD</code> macro definitions. Based on those I can
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handle four clock configurations: HSI, HSE, PLL HSI and PLL HSE.
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<pre>
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/* user LED ON when PA4 is high */
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#define LED_IOP A
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#define LED_PIN 4
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#define LED_ON 1
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/* 8MHz quartz, configure PLL at 24MHz */
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#define HSE 8000000
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#define PLL 6
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#define BAUD 9600
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#ifdef PLL
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# ifdef HSE
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# define CLOCK HSE / 2 * PLL
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# else /* HSI */
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# define CLOCK 8000000 / 2 * PLL
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# endif
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# if CLOCK < 16000000
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# error PLL output below 16MHz
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# endif
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#else
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# ifdef HSE
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# define CLOCK HSE
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# else /* HSI */
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# define CLOCK 8000000
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# endif
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#endif
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</pre>
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At compilation time there will be a check if the clock targeted is in
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the supported range of the chipset and a warning given if the baud rate
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generation is not accurate.
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<pre>
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#if CLOCK > 48000000
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# error clock frequency exceeds 48MHz
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#endif
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#if CLOCK % BAUD
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# warning baud rate not accurate at that clock frequency
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#endif
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</pre>
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I expand the definition of the Reset and Clock Control (RCC) peripheral
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to add the necessary bit fields.
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<pre>
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#define CAT( a, b) a##b
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#define HEXA( a) CAT( 0x, a)
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#define RCC ((volatile long *) 0x40021000)
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#define RCC_CR RCC[ 0]
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#define RCC_CR_HSION 0x00000001 /* 1: Internal High Speed clock enable */
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#define RCC_CR_HSEON 0x00010000 /* 16: External High Speed clock enable */
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#define RCC_CR_HSERDY 0x00020000 /* 17: External High Speed clock ready flag$
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#define RCC_CR_PLLON 0x01000000 /* 24: PLL enable */
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#define RCC_CR_PLLRDY 0x02000000 /* 25: PLL clock ready flag */
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#define RCC_CFGR RCC[ 1]
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#define RCC_CFGR_SW_MSK 0x00000003 /* 1-0: System clock SWitch Mask */
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#define RCC_CFGR_SW_HSE 0x00000001 /* 1-0: Switch to HSE as system clock */
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#define RCC_CFGR_SW_PLL 0x00000002 /* 1-0: Switch to PLL as system clock */
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#define RCC_CFGR_SWS_MSK 0x0000000C /* 3-2: System clock SWitch Status Mask$
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#define RCC_CFGR_SWS_HSE 0x00000004 /* 3-2: HSE used as system clock */
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#define RCC_CFGR_SWS_PLL 0x00000008 /* 3-2: PLL used as system clock */
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#define RCC_CFGR_PLLSRC 0x00010000
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#define RCC_CFGR_PLLSRC_HSI 0x00000000 /* HSI / 2 */
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#define RCC_CFGR_PLLSRC_HSE 0x00010000 /* HSE */
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#define RCC_CFGR_PLLXTPRE 0x00020000
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#define RCC_CFGR_PLLXTPRE_DIV1 0x00000000 /* HSE */
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#define RCC_CFGR_PLLXTPRE_DIV2 0x00020000 /* HSE / 2 */
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#define RCC_CFGR_PLLMUL_MSK (0x00F << 18)
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#define RCC_CFGR_PLLMUL( v) ((v - 2) << 18)
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#define RCC_AHBENR RCC[ 5]
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#define RCC_AHBENR_IOP( h) (1 << (17 + HEXA( h) - 0xA))
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#define RCC_APB2ENR RCC[ 6]
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#define RCC_APB2ENR_USART1EN 0x00004000 /* 14: USART1 clock enable */
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</pre>
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The code to configure the clocks follow the steps I have described
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before. The conditional compilation allows the generation of the four
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possible cases: HSI, HSE, PLL HSI and PLL HSE.
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<pre>
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/* By default SYSCLK == HSI [8MHZ] */
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#ifdef HSE
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/* Start HSE clock (8 MHz external oscillator) */
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RCC_CR |= RCC_CR_HSEON ;
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/* Wait for oscillator to stabilize */
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do {} while( (RCC_CR & RCC_CR_HSERDY) == 0) ;
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#endif
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#ifdef PLL
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/* Setup PLL HSx/2 * 6 [24MHz] */
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/* Default 0: PLL HSI/2 src, PLL MULL * 2 */
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# ifdef HSE
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RCC_CFGR = RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_DIV2 ;
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# endif
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RCC_CFGR |= RCC_CFGR_PLLMUL( PLL) ;
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RCC_CR |= RCC_CR_PLLON ;
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do {} while( (RCC_CR & RCC_CR_PLLRDY) == 0) ; /* Wait for PLL */
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/* Switch to PLL as system clock SYSCLK == PLL [24MHz] */
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MSK) | RCC_CFGR_SW_PLL ;
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do {} while( (RCC_CFGR & RCC_CFGR_SWS_MSK) != RCC_CFGR_SWS_PLL) ;
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#else
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# ifdef HSE
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/* Switch to HSE as system clock SYSCLK == HSE [8MHz] */
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MSK) | RCC_CFGR_SW_HSE ;
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do {} while( (RCC_CFGR & RCC_CFGR_SWS_MSK) != RCC_CFGR_SWS_HSE) ;
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# endif
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#endif
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#ifdef HSE
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/* Switch off HSI */
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RCC_CR &= ~RCC_CR_HSION ;
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#endif
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</pre>
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Systick reload value is calculated based on <code>CLOCK</code> constant value.
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<pre>
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SYSTICK_RVR = CLOCK / 8 - 1 ; /* HBA / 8 */
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</pre>
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Similarly, USART1 baud rate register is calculated based on <code>CLOCK</code>
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and <code>BAUD</code> constant value.
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<pre>
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USART1[ BRR] = CLOCK / BAUD ; /* PCLK is default source */
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</pre>
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I add a debug print at the end of <code>init()</code> to display which clock
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configuration has been set.
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<pre>
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kputs(
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#ifdef PLL
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"PLL"
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#endif
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#ifdef HSE
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"HSE"
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#else
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"HSI"
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#endif
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"\n") ;
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</pre>
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<h2>Build and test</h2>
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To build, I first update the composition in Makefile.
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<pre>SRCS = startup.c clocks.c uptime.c</pre>
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Build complete successfully, this is for PLL HSE board configuration.
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<pre>
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$ make
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f030f4.elf from startup.o clocks.o uptime.o
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text data bss dec hex filename
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1901 0 12 1913 779 f030f4.elf
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f030f4.hex
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f030f4.bin
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</pre>
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I use a board with a 8 MHz quartz soldered on and test the four clock
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configuration.
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<h2>Checkpoint</h2>
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I have tuned the baud rate setting by using a higher frequency for the
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system clock. The clock tree is complex and I have only looked at a part
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of it. Nevertheless the implementation for the clock configuration give
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me some flexibility and ease of setup.
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<p>
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<a href="29_interrupt.html">Next</a>, I will implement interrupt driven
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transmission.
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<hr>© 2020-2024 Renaud Fivet
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</body>
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</html>
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