491 lines
17 KiB
C
491 lines
17 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2021 Evan Nemerson <evan@nemerson.com>
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*/
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#if !defined(SIMDE_X86_AVX512_CMPNEQ_H)
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#define SIMDE_X86_AVX512_CMPNEQ_H
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#include "types.h"
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#include "../avx2.h"
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#include "mov.h"
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#include "mov_mask.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm_cmpneq_epi8_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_cmpneq_epi8_mask(a, b);
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#else
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return ~simde_mm_movepi8_mask(simde_mm_cmpeq_epi8(a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epi8_mask
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#define _mm_cmpneq_epi8_mask(a, b) simde_mm_cmpneq_epi8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm_mask_cmpneq_epi8_mask(simde__mmask16 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_mask_cmpneq_epi8_mask(k1, a, b);
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#else
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return simde_mm_cmpneq_epi8_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epi8_mask
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#define _mm_mask_cmpneq_epi8_mask(a, b) simde_mm_mask_cmpneq_epi8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm_cmpneq_epu8_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_cmpneq_epu8_mask(a, b);
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#else
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return simde_mm_cmpneq_epi8_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epu8_mask
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#define _mm_cmpneq_epu8_mask(a, b) simde_mm_cmpneq_epu8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm_mask_cmpneq_epu8_mask(simde__mmask16 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_mask_cmpneq_epu8_mask(k1, a, b);
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#else
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return simde_mm_mask_cmpneq_epi8_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epu8_mask
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#define _mm_mask_cmpneq_epu8_mask(a, b) simde_mm_mask_cmpneq_epu8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_cmpneq_epi16_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_cmpneq_epi16_mask(a, b);
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#else
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return ~simde_mm_movepi16_mask(simde_mm_cmpeq_epi16(a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epi16_mask
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#define _mm_cmpneq_epi16_mask(a, b) simde_mm_cmpneq_epi16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_mask_cmpneq_epi16_mask(simde__mmask8 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_mask_cmpneq_epi16_mask(k1, a, b);
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#else
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return simde_mm_cmpneq_epi16_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epi16_mask
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#define _mm_mask_cmpneq_epi16_mask(a, b) simde_mm_mask_cmpneq_epi16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_cmpneq_epu16_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_cmpneq_epu16_mask(a, b);
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#else
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return simde_mm_cmpneq_epi16_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epu16_mask
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#define _mm_cmpneq_epu16_mask(a, b) simde_mm_cmpneq_epu16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_mask_cmpneq_epu16_mask(simde__mmask8 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm_mask_cmpneq_epu16_mask(k1, a, b);
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#else
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return simde_mm_mask_cmpneq_epi16_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epu16_mask
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#define _mm_mask_cmpneq_epu16_mask(a, b) simde_mm_mask_cmpneq_epu16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_cmpneq_epi32_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_cmpneq_epi32_mask(a, b);
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#else
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return (~simde_mm_movepi32_mask(simde_mm_cmpeq_epi32(a, b))) & 15;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epi32_mask
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#define _mm_cmpneq_epi32_mask(a, b) simde_mm_cmpneq_epi32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_mask_cmpneq_epi32_mask(simde__mmask8 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_mask_cmpneq_epi32_mask(k1, a, b);
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#else
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return simde_mm_cmpneq_epi32_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epi32_mask
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#define _mm_mask_cmpneq_epi32_mask(a, b) simde_mm_mask_cmpneq_epi32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_cmpneq_epu32_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_cmpneq_epu32_mask(a, b);
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#else
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return simde_mm_cmpneq_epi32_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epu32_mask
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#define _mm_cmpneq_epu32_mask(a, b) simde_mm_cmpneq_epu32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_mask_cmpneq_epu32_mask(simde__mmask8 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_mask_cmpneq_epu32_mask(k1, a, b);
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#else
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return simde_mm_mask_cmpneq_epi32_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epu32_mask
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#define _mm_mask_cmpneq_epu32_mask(a, b) simde_mm_mask_cmpneq_epu32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_cmpneq_epi64_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_cmpneq_epi64_mask(a, b);
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#else
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return (~simde_mm_movepi64_mask(simde_mm_cmpeq_epi64(a, b))) & 3;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epi64_mask
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#define _mm_cmpneq_epi64_mask(a, b) simde_mm_cmpneq_epi64_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_mask_cmpneq_epi64_mask(simde__mmask8 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_mask_cmpneq_epi64_mask(k1, a, b);
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#else
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return simde_mm_cmpneq_epi64_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epi64_mask
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#define _mm_mask_cmpneq_epi64_mask(a, b) simde_mm_mask_cmpneq_epi64_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_cmpneq_epu64_mask(simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_cmpneq_epu64_mask(a, b);
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#else
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return simde_mm_cmpneq_epi64_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_cmpneq_epu64_mask
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#define _mm_cmpneq_epu64_mask(a, b) simde_mm_cmpneq_epu64_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm_mask_cmpneq_epu64_mask(simde__mmask8 k1, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm_mask_cmpneq_epu64_mask(k1, a, b);
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#else
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return simde_mm_mask_cmpneq_epi64_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_cmpneq_epu64_mask
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#define _mm_mask_cmpneq_epu64_mask(a, b) simde_mm_mask_cmpneq_epu64_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask32
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simde_mm256_cmpneq_epi8_mask(simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_cmpneq_epi8_mask(a, b);
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#else
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return ~simde_mm256_movepi8_mask(simde_mm256_cmpeq_epi8(a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_cmpneq_epi8_mask
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#define _mm256_cmpneq_epi8_mask(a, b) simde_mm256_cmpneq_epi8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask32
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simde_mm256_mask_cmpneq_epi8_mask(simde__mmask32 k1, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_mask_cmpneq_epi8_mask(k1, a, b);
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#else
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return simde_mm256_cmpneq_epi8_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_cmpneq_epi8_mask
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#define _mm256_mask_cmpneq_epi8_mask(a, b) simde_mm256_mask_cmpneq_epi8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask32
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simde_mm256_cmpneq_epu8_mask(simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_cmpneq_epu8_mask(a, b);
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#else
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return simde_mm256_cmpneq_epi8_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_cmpneq_epu8_mask
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#define _mm256_cmpneq_epu8_mask(a, b) simde_mm256_cmpneq_epu8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask32
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simde_mm256_mask_cmpneq_epu8_mask(simde__mmask32 k1, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_mask_cmpneq_epu8_mask(k1, a, b);
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#else
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return simde_mm256_mask_cmpneq_epi8_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_cmpneq_epu8_mask
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#define _mm256_mask_cmpneq_epu8_mask(a, b) simde_mm256_mask_cmpneq_epu8_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm256_cmpneq_epi16_mask(simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_cmpneq_epi16_mask(a, b);
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#else
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return ~simde_mm256_movepi16_mask(simde_mm256_cmpeq_epi16(a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_cmpneq_epi16_mask
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#define _mm256_cmpneq_epi16_mask(a, b) simde_mm256_cmpneq_epi16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm256_mask_cmpneq_epi16_mask(simde__mmask16 k1, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_mask_cmpneq_epi16_mask(k1, a, b);
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#else
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return simde_mm256_cmpneq_epi16_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_cmpneq_epi16_mask
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#define _mm256_mask_cmpneq_epi16_mask(a, b) simde_mm256_mask_cmpneq_epi16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm256_cmpneq_epu16_mask(simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_cmpneq_epu16_mask(a, b);
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#else
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return simde_mm256_cmpneq_epi16_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_cmpneq_epu16_mask
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#define _mm256_cmpneq_epu16_mask(a, b) simde_mm256_cmpneq_epu16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask16
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simde_mm256_mask_cmpneq_epu16_mask(simde__mmask16 k1, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
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return _mm256_mask_cmpneq_epu16_mask(k1, a, b);
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#else
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return simde_mm256_mask_cmpneq_epi16_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_cmpneq_epu16_mask
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#define _mm256_mask_cmpneq_epu16_mask(a, b) simde_mm256_mask_cmpneq_epu16_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm256_cmpneq_epi32_mask(simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm256_cmpneq_epi32_mask(a, b);
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#else
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return (~simde_mm256_movepi32_mask(simde_mm256_cmpeq_epi32(a, b)));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm256_cmpneq_epi32_mask
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#define _mm256_cmpneq_epi32_mask(a, b) simde_mm256_cmpneq_epi32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm256_mask_cmpneq_epi32_mask(simde__mmask8 k1, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm256_mask_cmpneq_epi32_mask(k1, a, b);
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#else
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return simde_mm256_cmpneq_epi32_mask(a, b) & k1;
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_cmpneq_epi32_mask
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#define _mm256_mask_cmpneq_epi32_mask(a, b) simde_mm256_mask_cmpneq_epi32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
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simde_mm256_cmpneq_epu32_mask(simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm256_cmpneq_epu32_mask(a, b);
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#else
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return simde_mm256_cmpneq_epi32_mask(a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm256_cmpneq_epu32_mask
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#define _mm256_cmpneq_epu32_mask(a, b) simde_mm256_cmpneq_epu32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__mmask8
|
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simde_mm256_mask_cmpneq_epu32_mask(simde__mmask8 k1, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm256_mask_cmpneq_epu32_mask(k1, a, b);
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#else
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return simde_mm256_mask_cmpneq_epi32_mask(k1, a, b);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_cmpneq_epu32_mask
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#define _mm256_mask_cmpneq_epu32_mask(a, b) simde_mm256_mask_cmpneq_epu32_mask((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__mmask8
|
|
simde_mm256_cmpneq_epi64_mask(simde__m256i a, simde__m256i b) {
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|
#if defined(SIMDE_X86_AVX512VL_NATIVE)
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return _mm256_cmpneq_epi64_mask(a, b);
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#else
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return (~simde_mm256_movepi64_mask(simde_mm256_cmpeq_epi64(a, b))) & 15;
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|
#endif
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|
}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm256_cmpneq_epi64_mask
|
|
#define _mm256_cmpneq_epi64_mask(a, b) simde_mm256_cmpneq_epi64_mask((a), (b))
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__mmask8
|
|
simde_mm256_mask_cmpneq_epi64_mask(simde__mmask8 k1, simde__m256i a, simde__m256i b) {
|
|
#if defined(SIMDE_X86_AVX512VL_NATIVE)
|
|
return _mm256_mask_cmpneq_epi64_mask(k1, a, b);
|
|
#else
|
|
return simde_mm256_cmpneq_epi64_mask(a, b) & k1;
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm256_mask_cmpneq_epi64_mask
|
|
#define _mm256_mask_cmpneq_epi64_mask(a, b) simde_mm256_mask_cmpneq_epi64_mask((a), (b))
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__mmask8
|
|
simde_mm256_cmpneq_epu64_mask(simde__m256i a, simde__m256i b) {
|
|
#if defined(SIMDE_X86_AVX512VL_NATIVE)
|
|
return _mm256_cmpneq_epu64_mask(a, b);
|
|
#else
|
|
return simde_mm256_cmpneq_epi64_mask(a, b);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm256_cmpneq_epu64_mask
|
|
#define _mm256_cmpneq_epu64_mask(a, b) simde_mm256_cmpneq_epu64_mask((a), (b))
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__mmask8
|
|
simde_mm256_mask_cmpneq_epu64_mask(simde__mmask8 k1, simde__m256i a, simde__m256i b) {
|
|
#if defined(SIMDE_X86_AVX512VL_NATIVE)
|
|
return _mm256_mask_cmpneq_epu64_mask(k1, a, b);
|
|
#else
|
|
return simde_mm256_mask_cmpneq_epi64_mask(k1, a, b);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm256_mask_cmpneq_epu64_mask
|
|
#define _mm256_mask_cmpneq_epu64_mask(a, b) simde_mm256_mask_cmpneq_epu64_mask((a), (b))
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|
#endif
|
|
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SIMDE_END_DECLS_
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HEDLEY_DIAGNOSTIC_POP
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#endif /* !defined(SIMDE_X86_AVX512_CMPNEQ_H) */
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