212 lines
7.1 KiB
C
212 lines
7.1 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2021 Evan Nemerson <evan@nemerson.com>
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*/
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#if !defined(SIMDE_ARM_NEON_SUBHN_H)
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#define SIMDE_ARM_NEON_SUBHN_H
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#include "sub.h"
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#include "shr_n.h"
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#include "movn.h"
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#include "reinterpret.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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SIMDE_FUNCTION_ATTRIBUTES
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simde_int8x8_t
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simde_vsubhn_s16(simde_int16x8_t a, simde_int16x8_t b) {
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vsubhn_s16(a, b);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
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simde_int8x8_private r_;
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simde_int8x16_private tmp_ =
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simde_int8x16_to_private(
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simde_vreinterpretq_s8_s16(
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simde_vsubq_s16(a, b)
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)
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);
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#if SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 1, 3, 5, 7, 9, 11, 13, 15);
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#else
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2, 4, 6, 8, 10, 12, 14);
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#endif
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return simde_int8x8_from_private(r_);
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#else
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return simde_vmovn_s16(simde_vshrq_n_s16(simde_vsubq_s16(a, b), 8));
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vsubhn_s16
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#define vsubhn_s16(a, b) simde_vsubhn_s16((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_int16x4_t
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simde_vsubhn_s32(simde_int32x4_t a, simde_int32x4_t b) {
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vsubhn_s32(a, b);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
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simde_int16x4_private r_;
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simde_int16x8_private tmp_ =
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simde_int16x8_to_private(
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simde_vreinterpretq_s16_s32(
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simde_vsubq_s32(a, b)
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)
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);
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#if SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 1, 3, 5, 7);
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#else
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2, 4, 6);
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#endif
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return simde_int16x4_from_private(r_);
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#else
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return simde_vmovn_s32(simde_vshrq_n_s32(simde_vsubq_s32(a, b), 16));
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vsubhn_s32
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#define vsubhn_s32(a, b) simde_vsubhn_s32((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_int32x2_t
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simde_vsubhn_s64(simde_int64x2_t a, simde_int64x2_t b) {
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vsubhn_s64(a, b);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
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simde_int32x2_private r_;
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simde_int32x4_private tmp_ =
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simde_int32x4_to_private(
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simde_vreinterpretq_s32_s64(
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simde_vsubq_s64(a, b)
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)
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);
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#if SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 1, 3);
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#else
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2);
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#endif
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return simde_int32x2_from_private(r_);
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#else
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return simde_vmovn_s64(simde_vshrq_n_s64(simde_vsubq_s64(a, b), 32));
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vsubhn_s64
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#define vsubhn_s64(a, b) simde_vsubhn_s64((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint8x8_t
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simde_vsubhn_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vsubhn_u16(a, b);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
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simde_uint8x8_private r_;
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simde_uint8x16_private tmp_ =
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simde_uint8x16_to_private(
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simde_vreinterpretq_u8_u16(
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simde_vsubq_u16(a, b)
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)
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);
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#if SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 1, 3, 5, 7, 9, 11, 13, 15);
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#else
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2, 4, 6, 8, 10, 12, 14);
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#endif
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return simde_uint8x8_from_private(r_);
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#else
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return simde_vmovn_u16(simde_vshrq_n_u16(simde_vsubq_u16(a, b), 8));
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vsubhn_u16
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#define vsubhn_u16(a, b) simde_vsubhn_u16((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint16x4_t
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simde_vsubhn_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vsubhn_u32(a, b);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
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simde_uint16x4_private r_;
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simde_uint16x8_private tmp_ =
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simde_uint16x8_to_private(
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simde_vreinterpretq_u16_u32(
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simde_vsubq_u32(a, b)
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)
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);
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#if SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 1, 3, 5, 7);
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#else
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2, 4, 6);
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#endif
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return simde_uint16x4_from_private(r_);
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#else
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return simde_vmovn_u32(simde_vshrq_n_u32(simde_vsubq_u32(a, b), 16));
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vsubhn_u32
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#define vsubhn_u32(a, b) simde_vsubhn_u32((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x2_t
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simde_vsubhn_u64(simde_uint64x2_t a, simde_uint64x2_t b) {
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vsubhn_u64(a, b);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
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simde_uint32x2_private r_;
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simde_uint32x4_private tmp_ =
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simde_uint32x4_to_private(
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simde_vreinterpretq_u32_u64(
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simde_vsubq_u64(a, b)
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)
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);
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#if SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 1, 3);
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#else
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r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2);
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#endif
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return simde_uint32x2_from_private(r_);
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#else
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return simde_vmovn_u64(simde_vshrq_n_u64(simde_vsubq_u64(a, b), 32));
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vsubhn_u64
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#define vsubhn_u64(a, b) simde_vsubhn_u64((a), (b))
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#endif
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SIMDE_END_DECLS_
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HEDLEY_DIAGNOSTIC_POP
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#endif /* !defined(SIMDE_ARM_NEON_SUBHN_H) */
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