430 lines
15 KiB
C
430 lines
15 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2021 Evan Nemerson <evan@nemerson.com>
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*/
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#if !defined(SIMDE_MIPS_MSA_ADDS_H)
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#define SIMDE_MIPS_MSA_ADDS_H
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#include "types.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v16i8
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simde_msa_adds_s_b(simde_v16i8 a, simde_v16i8 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_s_b(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_s8(a, b);
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#elif defined(SIMDE_POWER_ALTIVEC_P6)
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return vec_adds(a, b);
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#else
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simde_v16i8_private
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a_ = simde_v16i8_to_private(a),
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b_ = simde_v16i8_to_private(b),
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r_;
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#if defined(SIMDE_WASM_SIMD128_NATIVE)
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r_.v128 = wasm_i8x16_add_sat(a_.v128, b_.v128);
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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r_.m128i = _mm_adds_epi8(a_.m128i, b_.m128i);
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#elif defined(SIMDE_VECTOR_SCALAR)
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uint8_t au SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(au), a_.values);
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uint8_t bu SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(bu), b_.values);
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uint8_t ru SIMDE_VECTOR(16) = au + bu;
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au = (au >> 7) + INT8_MAX;
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uint8_t m SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(m), HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au ^ bu) | ~(bu ^ ru)) < 0);
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r_.values = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au & ~m) | (ru & m));
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_math_adds_i8(a_.values[i], b_.values[i]);
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}
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#endif
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return simde_v16i8_from_private(r_);
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#endif
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}
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#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
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#undef __msa_adds_s_b
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#define __msa_adds_s_b(a, b) simde_msa_adds_s_b((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v8i16
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simde_msa_adds_s_h(simde_v8i16 a, simde_v8i16 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_s_h(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_s16(a, b);
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#elif defined(SIMDE_POWER_ALTIVEC_P6)
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return vec_adds(a, b);
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#else
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simde_v8i16_private
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a_ = simde_v8i16_to_private(a),
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b_ = simde_v8i16_to_private(b),
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r_;
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#if defined(SIMDE_WASM_SIMD128_NATIVE)
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r_.v128 = wasm_i16x8_add_sat(a_.v128, b_.v128);
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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r_.m128i = _mm_adds_epi16(a_.m128i, b_.m128i);
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#elif defined(SIMDE_VECTOR_SCALAR)
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uint16_t au SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(au), a_.values);
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uint16_t bu SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(bu), b_.values);
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uint16_t ru SIMDE_VECTOR(16) = au + bu;
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au = (au >> 15) + INT16_MAX;
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uint16_t m SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(m), HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au ^ bu) | ~(bu ^ ru)) < 0);
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r_.values = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au & ~m) | (ru & m));
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_math_adds_i16(a_.values[i], b_.values[i]);
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}
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#endif
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return simde_v8i16_from_private(r_);
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#endif
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}
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#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
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#undef __msa_adds_s_h
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#define __msa_adds_s_h(a, b) simde_msa_adds_s_h((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v4i32
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simde_msa_adds_s_w(simde_v4i32 a, simde_v4i32 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_s_w(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_s32(a, b);
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#elif defined(SIMDE_POWER_ALTIVEC_P6)
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return vec_adds(a, b);
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#else
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simde_v4i32_private
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a_ = simde_v4i32_to_private(a),
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b_ = simde_v4i32_to_private(b),
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r_;
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#if defined(SIMDE_X86_SSE2_NATIVE)
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/* https://stackoverflow.com/a/56544654/501126 */
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const __m128i int_max = _mm_set1_epi32(INT32_MAX);
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/* normal result (possibly wraps around) */
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const __m128i sum = _mm_add_epi32(a_.m128i, b_.m128i);
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/* If result saturates, it has the same sign as both a and b */
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const __m128i sign_bit = _mm_srli_epi32(a_.m128i, 31); /* shift sign to lowest bit */
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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const __m128i overflow = _mm_ternarylogic_epi32(a_.m128i, b_.m128i, sum, 0x42);
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#else
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const __m128i sign_xor = _mm_xor_si128(a_.m128i, b_.m128i);
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const __m128i overflow = _mm_andnot_si128(sign_xor, _mm_xor_si128(a_.m128i, sum));
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#endif
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#if defined(SIMDE_X86_AVX512DQ_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
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r_.m128i = _mm_mask_add_epi32(sum, _mm_movepi32_mask(overflow), int_max, sign_bit);
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#else
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const __m128i saturated = _mm_add_epi32(int_max, sign_bit);
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#if defined(SIMDE_X86_SSE4_1_NATIVE)
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r_.m128i =
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_mm_castps_si128(
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_mm_blendv_ps(
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_mm_castsi128_ps(sum),
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_mm_castsi128_ps(saturated),
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_mm_castsi128_ps(overflow)
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)
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);
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#else
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const __m128i overflow_mask = _mm_srai_epi32(overflow, 31);
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r_.m128i =
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_mm_or_si128(
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_mm_and_si128(overflow_mask, saturated),
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_mm_andnot_si128(overflow_mask, sum)
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);
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#endif
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#endif
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#elif defined(SIMDE_VECTOR_SCALAR)
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uint32_t au SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(au), a_.values);
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uint32_t bu SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(bu), b_.values);
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uint32_t ru SIMDE_VECTOR(16) = au + bu;
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au = (au >> 31) + INT32_MAX;
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uint32_t m SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(m), HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au ^ bu) | ~(bu ^ ru)) < 0);
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r_.values = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au & ~m) | (ru & m));
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_math_adds_i32(a_.values[i], b_.values[i]);
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}
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#endif
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return simde_v4i32_from_private(r_);
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#endif
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}
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#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
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#undef __msa_adds_s_w
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#define __msa_adds_s_w(a, b) simde_msa_adds_s_w((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v2i64
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simde_msa_adds_s_d(simde_v2i64 a, simde_v2i64 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_s_d(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_s64(a, b);
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#else
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simde_v2i64_private
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a_ = simde_v2i64_to_private(a),
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b_ = simde_v2i64_to_private(b),
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r_;
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#if defined(SIMDE_X86_SSE4_1_NATIVE)
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/* https://stackoverflow.com/a/56544654/501126 */
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const __m128i int_max = _mm_set1_epi64x(INT64_MAX);
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/* normal result (possibly wraps around) */
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const __m128i sum = _mm_add_epi64(a_.m128i, b_.m128i);
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/* If result saturates, it has the same sign as both a and b */
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const __m128i sign_bit = _mm_srli_epi64(a_.m128i, 63); /* shift sign to lowest bit */
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#if defined(SIMDE_X86_AVX512VL_NATIVE)
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const __m128i overflow = _mm_ternarylogic_epi64(a_.m128i, b_.m128i, sum, 0x42);
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#else
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const __m128i sign_xor = _mm_xor_si128(a_.m128i, b_.m128i);
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const __m128i overflow = _mm_andnot_si128(sign_xor, _mm_xor_si128(a_.m128i, sum));
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#endif
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512DQ_NATIVE)
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r_.m128i = _mm_mask_add_epi64(sum, _mm_movepi64_mask(overflow), int_max, sign_bit);
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#else
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const __m128i saturated = _mm_add_epi64(int_max, sign_bit);
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r_.m128i =
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_mm_castpd_si128(
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_mm_blendv_pd(
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_mm_castsi128_pd(sum),
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_mm_castsi128_pd(saturated),
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_mm_castsi128_pd(overflow)
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)
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);
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#endif
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#elif defined(SIMDE_VECTOR_SCALAR)
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uint64_t au SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(au), a_.values);
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uint64_t bu SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(bu), b_.values);
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uint64_t ru SIMDE_VECTOR(16) = au + bu;
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au = (au >> 63) + INT64_MAX;
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uint64_t m SIMDE_VECTOR(16) = HEDLEY_REINTERPRET_CAST(__typeof__(m), HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au ^ bu) | ~(bu ^ ru)) < 0);
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r_.values = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (au & ~m) | (ru & m));
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_math_adds_i64(a_.values[i], b_.values[i]);
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}
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#endif
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return simde_v2i64_from_private(r_);
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#endif
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}
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#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
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#undef __msa_adds_s_d
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#define __msa_adds_s_d(a, b) simde_msa_adds_s_d((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v16u8
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simde_msa_adds_u_b(simde_v16u8 a, simde_v16u8 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_u_b(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_u8(a, b);
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#elif defined(SIMDE_POWER_ALTIVEC_P6)
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return vec_adds(a, b);
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#else
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simde_v16u8_private
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a_ = simde_v16u8_to_private(a),
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b_ = simde_v16u8_to_private(b),
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r_;
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#if defined(SIMDE_WASM_SIMD128_NATIVE)
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r_.v128 = wasm_u8x16_add_sat(a_.v128, b_.v128);
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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r_.m128i = _mm_adds_epu8(a_.m128i, b_.m128i);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT)
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r_.values = a_.values + b_.values;
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r_.values |= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values < a_.values);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_math_adds_u8(a_.values[i], b_.values[i]);
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}
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#endif
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return simde_v16u8_from_private(r_);
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#endif
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}
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#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
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#undef __msa_adds_u_b
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#define __msa_adds_u_b(a, b) simde_msa_adds_u_b((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v8u16
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simde_msa_adds_u_h(simde_v8u16 a, simde_v8u16 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_u_h(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_u16(a, b);
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#elif defined(SIMDE_POWER_ALTIVEC_P6)
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return vec_adds(a, b);
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#else
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simde_v8u16_private
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a_ = simde_v8u16_to_private(a),
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b_ = simde_v8u16_to_private(b),
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r_;
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#if defined(SIMDE_WASM_SIMD128_NATIVE)
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r_.v128 = wasm_u16x8_add_sat(a_.v128, b_.v128);
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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r_.m128i = _mm_adds_epu16(a_.m128i, b_.m128i);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT)
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r_.values = a_.values + b_.values;
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r_.values |= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values < a_.values);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_math_adds_u16(a_.values[i], b_.values[i]);
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}
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#endif
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return simde_v8u16_from_private(r_);
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#endif
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}
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#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
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#undef __msa_adds_u_h
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#define __msa_adds_u_h(a, b) simde_msa_adds_u_h((a), (b))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_v4u32
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simde_msa_adds_u_w(simde_v4u32 a, simde_v4u32 b) {
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#if defined(SIMDE_MIPS_MSA_NATIVE)
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return __msa_adds_u_w(a, b);
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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return vqaddq_u32(a, b);
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#elif defined(SIMDE_POWER_ALTIVEC_P6)
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return vec_adds(a, b);
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#else
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simde_v4u32_private
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a_ = simde_v4u32_to_private(a),
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b_ = simde_v4u32_to_private(b),
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r_;
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#if defined(SIMDE_X86_SSE4_1_NATIVE)
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#if defined(__AVX512VL__)
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__m128i notb = _mm_ternarylogic_epi32(b, b, b, 0x0f);
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#else
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__m128i notb = _mm_xor_si128(b_.m128i, _mm_set1_epi32(~INT32_C(0)));
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#endif
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r_.m128i =
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_mm_add_epi32(
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b_.m128i,
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_mm_min_epu32(
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a_.m128i,
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notb
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)
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);
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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const __m128i sum = _mm_add_epi32(a_.m128i, b_.m128i);
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const __m128i i32min = _mm_set1_epi32(INT32_MIN);
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a_.m128i = _mm_xor_si128(a_.m128i, i32min);
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r_.m128i = _mm_or_si128(_mm_cmpgt_epi32(a_.m128i, _mm_xor_si128(i32min, sum)), sum);
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#elif defined(SIMDE_VECTOR_SUBSCRIPT)
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r_.values = a_.values + b_.values;
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r_.values |= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values < a_.values);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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|
r_.values[i] = simde_math_adds_u32(a_.values[i], b_.values[i]);
|
|
}
|
|
#endif
|
|
|
|
return simde_v4u32_from_private(r_);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
|
|
#undef __msa_adds_u_w
|
|
#define __msa_adds_u_w(a, b) simde_msa_adds_u_w((a), (b))
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde_v2u64
|
|
simde_msa_adds_u_d(simde_v2u64 a, simde_v2u64 b) {
|
|
#if defined(SIMDE_MIPS_MSA_NATIVE)
|
|
return __msa_adds_u_d(a, b);
|
|
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
|
return vqaddq_u64(a, b);
|
|
#else
|
|
simde_v2u64_private
|
|
a_ = simde_v2u64_to_private(a),
|
|
b_ = simde_v2u64_to_private(b),
|
|
r_;
|
|
|
|
#if defined(SIMDE_VECTOR_SUBSCRIPT)
|
|
r_.values = a_.values + b_.values;
|
|
r_.values |= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values < a_.values);
|
|
#else
|
|
SIMDE_VECTORIZE
|
|
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
|
r_.values[i] = simde_math_adds_u64(a_.values[i], b_.values[i]);
|
|
}
|
|
#endif
|
|
|
|
return simde_v2u64_from_private(r_);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_MIPS_MSA_ENABLE_NATIVE_ALIASES)
|
|
#undef __msa_adds_u_d
|
|
#define __msa_adds_u_d(a, b) simde_msa_adds_u_d((a), (b))
|
|
#endif
|
|
|
|
SIMDE_END_DECLS_
|
|
HEDLEY_DIAGNOSTIC_POP
|
|
|
|
#endif /* !defined(SIMDE_MIPS_MSA_ADDS_H) */
|