270 lines
8.8 KiB
C
270 lines
8.8 KiB
C
#if !defined(SIMDE_X86_AVX512_DPWSSD_H)
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#define SIMDE_X86_AVX512_DPWSSD_H
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#include "types.h"
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#include "mov.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m128i
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simde_mm_dpwssd_epi32(simde__m128i src, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm_dpwssd_epi32(src, a, b);
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#else
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simde__m128i_private
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src_ = simde__m128i_to_private(src),
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a_ = simde__m128i_to_private(a),
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b_ = simde__m128i_to_private(b);
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#if defined(SIMDE_SHUFFLE_VECTOR_) && defined(SIMDE_CONVERT_VECTOR_)
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int32_t x1_ SIMDE_VECTOR(32);
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int32_t x2_ SIMDE_VECTOR(32);
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simde__m128i_private
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r1_[2],
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r2_[2];
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a_.i16 =
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SIMDE_SHUFFLE_VECTOR_(
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16, 16,
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a_.i16, a_.i16,
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0, 2, 4, 6,
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1, 3, 5, 7
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);
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b_.i16 =
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SIMDE_SHUFFLE_VECTOR_(
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16, 16,
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b_.i16, b_.i16,
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0, 2, 4, 6,
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1, 3, 5, 7
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);
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SIMDE_CONVERT_VECTOR_(x1_, a_.i16);
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SIMDE_CONVERT_VECTOR_(x2_, b_.i16);
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simde_memcpy(&r1_, &x1_, sizeof(x1_));
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simde_memcpy(&r2_, &x2_, sizeof(x2_));
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src_.i32 +=
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(r1_[0].i32 * r2_[0].i32) +
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(r1_[1].i32 * r2_[1].i32);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(a_.u16) / sizeof(a_.i16[0])) ; i++) {
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src_.i32[i / 2] += HEDLEY_STATIC_CAST(int32_t, a_.i16[i]) * HEDLEY_STATIC_CAST(int32_t, b_.i16[i]);
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}
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#endif
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return simde__m128i_from_private(src_);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm_dpwssd_epi32
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#define _mm_dpwssd_epi32(src, a, b) simde_mm_dpwssd_epi32(src, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m128i
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simde_mm_mask_dpwssd_epi32(simde__m128i src, simde__mmask8 k, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm_mask_dpwssd_epi32(src, k, a, b);
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#else
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return simde_mm_mask_mov_epi32(src, k, simde_mm_dpwssd_epi32(src, a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm_mask_dpwssd_epi32
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#define _mm_mask_dpwssd_epi32(src, k, a, b) simde_mm_mask_dpwssd_epi32(src, k, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m128i
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simde_mm_maskz_dpwssd_epi32(simde__mmask8 k, simde__m128i src, simde__m128i a, simde__m128i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm_maskz_dpwssd_epi32(k, src, a, b);
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#else
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return simde_mm_maskz_mov_epi32(k, simde_mm_dpwssd_epi32(src, a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm_maskz_dpwssd_epi32
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#define _mm_maskz_dpwssd_epi32(k, src, a, b) simde_mm_maskz_dpwssd_epi32(k, src, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m256i
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simde_mm256_dpwssd_epi32(simde__m256i src, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm256_dpwssd_epi32(src, a, b);
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#else
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simde__m256i_private
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src_ = simde__m256i_to_private(src),
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a_ = simde__m256i_to_private(a),
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b_ = simde__m256i_to_private(b);
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#if defined(SIMDE_SHUFFLE_VECTOR_) && defined(SIMDE_CONVERT_VECTOR_)
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int32_t x1_ SIMDE_VECTOR(64);
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int32_t x2_ SIMDE_VECTOR(64);
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simde__m256i_private
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r1_[2],
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r2_[2];
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a_.i16 =
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SIMDE_SHUFFLE_VECTOR_(
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16, 32,
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a_.i16, a_.i16,
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0, 2, 4, 6, 8, 10, 12, 14,
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1, 3, 5, 7, 9, 11, 13, 15
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);
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b_.i16 =
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SIMDE_SHUFFLE_VECTOR_(
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16, 32,
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b_.i16, b_.i16,
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0, 2, 4, 6, 8, 10, 12, 14,
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1, 3, 5, 7, 9, 11, 13, 15
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);
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SIMDE_CONVERT_VECTOR_(x1_, a_.i16);
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SIMDE_CONVERT_VECTOR_(x2_, b_.i16);
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simde_memcpy(&r1_, &x1_, sizeof(x1_));
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simde_memcpy(&r2_, &x2_, sizeof(x2_));
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src_.i32 +=
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(r1_[0].i32 * r2_[0].i32) +
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(r1_[1].i32 * r2_[1].i32);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(a_.u16) / sizeof(a_.i16[0])) ; i++) {
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src_.i32[i / 2] += HEDLEY_STATIC_CAST(int32_t, a_.i16[i]) * HEDLEY_STATIC_CAST(int32_t, b_.i16[i]);
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}
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#endif
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return simde__m256i_from_private(src_);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm256_dpwssd_epi32
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#define _mm256_dpwssd_epi32(src, a, b) simde_mm256_dpwssd_epi32(src, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m256i
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simde_mm256_mask_dpwssd_epi32(simde__m256i src, simde__mmask8 k, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm256_mask_dpwssd_epi32(src, k, a, b);
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#else
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return simde_mm256_mask_mov_epi32(src, k, simde_mm256_dpwssd_epi32(src, a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm256_mask_dpwssd_epi32
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#define _mm256_mask_dpwssd_epi32(src, k, a, b) simde_mm256_mask_dpwssd_epi32(src, k, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m256i
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simde_mm256_maskz_dpwssd_epi32(simde__mmask8 k, simde__m256i src, simde__m256i a, simde__m256i b) {
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#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm256_maskz_dpwssd_epi32(k, src, a, b);
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#else
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return simde_mm256_maskz_mov_epi32(k, simde_mm256_dpwssd_epi32(src, a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm256_maskz_dpwssd_epi32
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#define _mm256_maskz_dpwssd_epi32(k, src, a, b) simde_mm256_maskz_dpwssd_epi32(k, src, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_dpwssd_epi32(simde__m512i src, simde__m512i a, simde__m512i b) {
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#if defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm512_dpwssd_epi32(src, a, b);
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#else
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simde__m512i_private
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src_ = simde__m512i_to_private(src),
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a_ = simde__m512i_to_private(a),
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b_ = simde__m512i_to_private(b);
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#if defined(SIMDE_SHUFFLE_VECTOR_) && defined(SIMDE_CONVERT_VECTOR_)
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int32_t x1_ SIMDE_VECTOR(128);
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int32_t x2_ SIMDE_VECTOR(128);
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simde__m512i_private
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r1_[2],
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r2_[2];
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a_.i16 =
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SIMDE_SHUFFLE_VECTOR_(
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16, 64,
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a_.i16, a_.i16,
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0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
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1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31
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);
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b_.i16 =
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SIMDE_SHUFFLE_VECTOR_(
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16, 64,
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b_.i16, b_.i16,
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0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
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1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31
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);
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SIMDE_CONVERT_VECTOR_(x1_, a_.i16);
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SIMDE_CONVERT_VECTOR_(x2_, b_.i16);
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simde_memcpy(&r1_, &x1_, sizeof(x1_));
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simde_memcpy(&r2_, &x2_, sizeof(x2_));
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src_.i32 +=
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(r1_[0].i32 * r2_[0].i32) +
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(r1_[1].i32 * r2_[1].i32);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(a_.u16) / sizeof(a_.i16[0])) ; i++) {
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src_.i32[i / 2] += HEDLEY_STATIC_CAST(int32_t, a_.i16[i]) * HEDLEY_STATIC_CAST(int32_t, b_.i16[i]);
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}
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#endif
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return simde__m512i_from_private(src_);
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#endif
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}
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#if defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm512_dpwssd_epi32
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#define _mm512_dpwssd_epi32(src, a, b) simde_mm512_dpwssd_epi32(src, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_mask_dpwssd_epi32(simde__m512i src, simde__mmask16 k, simde__m512i a, simde__m512i b) {
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#if defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm512_mask_dpwssd_epi32(src, k, a, b);
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#else
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return simde_mm512_mask_mov_epi32(src, k, simde_mm512_dpwssd_epi32(src, a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_dpwssd_epi32
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#define _mm512_mask_dpwssd_epi32(src, k, a, b) simde_mm512_mask_dpwssd_epi32(src, k, a, b)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_maskz_dpwssd_epi32(simde__mmask16 k, simde__m512i src, simde__m512i a, simde__m512i b) {
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#if defined(SIMDE_X86_AVX512VNNI_NATIVE)
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return _mm512_maskz_dpwssd_epi32(k, src, a, b);
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#else
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return simde_mm512_maskz_mov_epi32(k, simde_mm512_dpwssd_epi32(src, a, b));
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#endif
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}
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#if defined(SIMDE_X86_AVX512VNNI_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_dpwssd_epi32
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#define _mm512_maskz_dpwssd_epi32(k, src, a, b) simde_mm512_maskz_dpwssd_epi32(k, src, a, b)
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#endif
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SIMDE_END_DECLS_
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HEDLEY_DIAGNOSTIC_POP
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#endif /* !defined(SIMDE_X86_AVX512_DPWSSD_H) */
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