485 lines
18 KiB
C
485 lines
18 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2020 Evan Nemerson <evan@nemerson.com>
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* 2020 Christopher Moore <moore@free.fr>
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*/
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#if !defined(SIMDE_X86_AVX512_INSERT_H)
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#define SIMDE_X86_AVX512_INSERT_H
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#include "types.h"
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#include "mov.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512
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simde_mm512_insertf32x4 (simde__m512 a, simde__m128 b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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simde__m512 r;
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SIMDE_CONSTIFY_4_(_mm512_insertf32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, a, b);
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return r;
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#else
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simde__m512_private a_ = simde__m512_to_private(a);
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a_.m128[imm8 & 3] = b;
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return simde__m512_from_private(a_);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_insertf32x4
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#define _mm512_insertf32x4(a, b, imm8) simde_mm512_insertf32x4(a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512
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simde_mm512_mask_insertf32x4 (simde__m512 src, simde__mmask16 k, simde__m512 a, simde__m128 b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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simde__m512 r;
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#if defined(SIMDE_X86_AVX512F_NATIVE) && (!defined(HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(8,0,0))
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SIMDE_CONSTIFY_4_(_mm512_mask_insertf32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, src, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_4_(simde_mm512_insertf32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, a, b);
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return simde_mm512_mask_mov_ps(src, k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_insertf32x4
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#define _mm512_mask_insertf32x4(src, k, a, b, imm8) simde_mm512_mask_insertf32x4(src, k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512
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simde_mm512_maskz_insertf32x4 (simde__mmask16 k, simde__m512 a, simde__m128 b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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simde__m512 r;
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#if defined(SIMDE_X86_AVX512F_NATIVE) && (!defined(HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(8,0,0))
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SIMDE_CONSTIFY_4_(_mm512_maskz_insertf32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_4_(simde_mm512_insertf32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, a, b);
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return simde_mm512_maskz_mov_ps(k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_insertf32x4
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#define _mm512_maskz_insertf32x4(k, a, b, imm8) simde_mm512_maskz_insertf32x4(k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512d
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simde_mm512_insertf64x4 (simde__m512d a, simde__m256d b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 1) {
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simde__m512d_private a_ = simde__m512d_to_private(a);
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a_.m256d[imm8 & 1] = b;
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return simde__m512d_from_private(a_);
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}
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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#define simde_mm512_insertf64x4(a, b, imm8) _mm512_insertf64x4(a, b, imm8)
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#endif
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_insertf64x4
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#define _mm512_insertf64x4(a, b, imm8) simde_mm512_insertf64x4(a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512d
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simde_mm512_mask_insertf64x4 (simde__m512d src, simde__mmask8 k, simde__m512d a, simde__m256d b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 1) {
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simde__m512d r;
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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SIMDE_CONSTIFY_2_(_mm512_mask_insertf64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, src, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_2_(simde_mm512_insertf64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, a, b);
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return simde_mm512_mask_mov_pd(src, k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_insertf64x4
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#define _mm512_mask_insertf64x4(src, k, a, b, imm8) simde_mm512_mask_insertf64x4(src, k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512d
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simde_mm512_maskz_insertf64x4 (simde__mmask8 k, simde__m512d a, simde__m256d b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 1) {
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simde__m512d r;
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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SIMDE_CONSTIFY_2_(_mm512_maskz_insertf64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_2_(simde_mm512_insertf64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, a, b);
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return simde_mm512_maskz_mov_pd(k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_insertf64x4
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#define _mm512_maskz_insertf64x4(k, a, b, imm8) simde_mm512_maskz_insertf64x4(k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_inserti32x4 (simde__m512i a, simde__m128i b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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simde__m512i_private a_ = simde__m512i_to_private(a);
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a_.m128i[imm8 & 3] = b;
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return simde__m512i_from_private(a_);
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}
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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#define simde_mm512_inserti32x4(a, b, imm8) _mm512_inserti32x4(a, b, imm8)
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#endif
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_inserti32x4
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#define _mm512_inserti32x4(a, b, imm8) simde_mm512_inserti32x4(a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_mask_inserti32x4 (simde__m512i src, simde__mmask16 k, simde__m512i a, simde__m128i b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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simde__m512i r;
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#if defined(SIMDE_X86_AVX512F_NATIVE) && (!defined(HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(8,0,0))
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SIMDE_CONSTIFY_4_(_mm512_mask_inserti32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, src, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_4_(simde_mm512_inserti32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, a, b);
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return simde_mm512_mask_mov_epi32(src, k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_inserti32x4
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#define _mm512_mask_inserti32x4(src, k, a, b, imm8) simde_mm512_mask_inserti32x4(src, k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_maskz_inserti32x4 (simde__mmask16 k, simde__m512i a, simde__m128i b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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simde__m512i r;
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#if defined(SIMDE_X86_AVX512F_NATIVE) && (!defined(HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(8,0,0))
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SIMDE_CONSTIFY_4_(_mm512_maskz_inserti32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_4_(simde_mm512_inserti32x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, a, b);
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return simde_mm512_maskz_mov_epi32(k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_inserti32x4
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#define _mm512_maskz_inserti32x4(k, a, b, imm8) simde_mm512_maskz_inserti32x4(k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_inserti64x4 (simde__m512i a, simde__m256i b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 1) {
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simde__m512i_private a_ = simde__m512i_to_private(a);
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a_.m256i[imm8 & 1] = b;
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return simde__m512i_from_private(a_);
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}
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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#define simde_mm512_inserti64x4(a, b, imm8) _mm512_inserti64x4(a, b, imm8)
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#endif
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_inserti64x4
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#define _mm512_inserti64x4(a, b, imm8) simde_mm512_inserti64x4(a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_mask_inserti64x4 (simde__m512i src, simde__mmask8 k, simde__m512i a, simde__m256i b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 2) {
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simde__m512i r;
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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SIMDE_CONSTIFY_2_(_mm512_mask_inserti64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, src, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_2_(simde_mm512_inserti64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, a, b);
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return simde_mm512_mask_mov_epi64(src, k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_inserti64x4
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#define _mm512_mask_inserti64x4(src, k, a, b, imm8) simde_mm512_mask_inserti64x4(src, k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512i
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simde_mm512_maskz_inserti64x4 (simde__mmask8 k, simde__m512i a, simde__m256i b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 2) {
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simde__m512i r;
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#if defined(SIMDE_X86_AVX512F_NATIVE)
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SIMDE_CONSTIFY_2_(_mm512_maskz_inserti64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, k, a, b);
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return r;
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#else
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SIMDE_CONSTIFY_2_(simde_mm512_inserti64x4, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, a, b);
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return simde_mm512_maskz_mov_epi64(k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_inserti64x4
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#define _mm512_maskz_inserti64x4(k, a, b, imm8) simde_mm512_maskz_inserti64x4(k, a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512
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simde_mm512_insertf32x8 (simde__m512 a, simde__m256 b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 1) {
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simde__m512_private a_ = simde__m512_to_private(a);
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a_.m256[imm8 & 1] = b;
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return simde__m512_from_private(a_);
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}
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#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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#define simde_mm512_insertf32x8(a, b, imm8) _mm512_insertf32x8(a, b, imm8)
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#endif
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#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
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#undef _mm512_insertf32x8
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#define _mm512_insertf32x8(a, b, imm8) simde_mm512_insertf32x8(a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512
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simde_mm512_mask_insertf32x8(simde__m512 src, simde__mmask16 k, simde__m512 a, simde__m256 b, const int imm8) {
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#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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simde__m512 r;
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SIMDE_CONSTIFY_2_(_mm512_mask_insertf32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, src, k, a, b);
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return r;
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#else
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simde__m512 r;
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SIMDE_CONSTIFY_2_(simde_mm512_insertf32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, a, b);
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return simde_mm512_mask_mov_ps(src, k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_insertf32x8
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#define _mm512_mask_insertf32x8(src, k, a, b, imm8) simde_mm512_mask_insertf32x8(src, k, a, b, imms8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512
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simde_mm512_maskz_insertf32x8(simde__mmask16 k, simde__m512 a, simde__m256 b, const int imm8) {
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#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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simde__m512 r;
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SIMDE_CONSTIFY_2_(_mm512_maskz_insertf32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, k, a, b);
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return r;
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#else
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simde__m512 r;
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SIMDE_CONSTIFY_2_(simde_mm512_insertf32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_ps ()), imm8, a, b);
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return simde_mm512_maskz_mov_ps(k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_insertf32x8
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#define _mm512_maskz_insertf32x8(k, a, b, imm8) simde_mm512_maskz_insertf32x8(k, a, b, imms8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512d
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simde_mm512_insertf64x2 (simde__m512d a, simde__m128d b, int imm8)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
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simde__m512d_private a_ = simde__m512d_to_private(a);
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a_.m128d[imm8 & 3] = b;
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return simde__m512d_from_private(a_);
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}
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#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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#define simde_mm512_insertf64x2(a, b, imm8) _mm512_insertf64x2(a, b, imm8)
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#endif
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#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
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#undef _mm512_insertf64x2
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#define _mm512_insertf64x2(a, b, imm8) simde_mm512_insertf64x2(a, b, imm8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512d
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simde_mm512_mask_insertf64x2(simde__m512d src, simde__mmask8 k, simde__m512d a, simde__m128d b, const int imm8) {
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#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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simde__m512d r;
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SIMDE_CONSTIFY_4_(_mm512_mask_insertf64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, src, k, a, b);
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return r;
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#else
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simde__m512d r;
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SIMDE_CONSTIFY_4_(simde_mm512_insertf64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, a, b);
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return simde_mm512_mask_mov_pd(src, k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
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#undef _mm512_mask_insertf64x2
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#define _mm512_mask_insertf64x2(src, k, a, b, imm8) simde_mm512_mask_insertf64x2(src, k, a, b, imms8)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde__m512d
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simde_mm512_maskz_insertf64x2(simde__mmask8 k, simde__m512d a, simde__m128d b, const int imm8) {
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#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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simde__m512d r;
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SIMDE_CONSTIFY_4_(_mm512_maskz_insertf64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, k, a, b);
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return r;
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#else
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simde__m512d r;
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SIMDE_CONSTIFY_4_(simde_mm512_insertf64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_pd ()), imm8, a, b);
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return simde_mm512_maskz_mov_pd(k, r);
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#endif
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}
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#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
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#undef _mm512_maskz_insertf64x2
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#define _mm512_maskz_insertf64x2(k, a, b, imm8) simde_mm512_maskz_insertf64x2(k, a, b, imms8)
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#endif
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|
|
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SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__m512i
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simde_mm512_inserti32x8 (simde__m512i a, simde__m256i b, int imm8)
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|
SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 1) {
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simde__m512i_private a_ = simde__m512i_to_private(a);
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|
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a_.m256i[imm8 & 1] = b;
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|
|
|
return simde__m512i_from_private(a_);
|
|
}
|
|
#if defined(SIMDE_X86_AVX512DQ_NATIVE)
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|
#define simde_mm512_inserti32x8(a, b, imm8) _mm512_inserti32x8(a, b, imm8)
|
|
#endif
|
|
#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm512_inserti32x8
|
|
#define _mm512_inserti32x8(a, b, imm8) simde_mm512_inserti32x8(a, b, imm8)
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__m512i
|
|
simde_mm512_mask_inserti32x8(simde__m512i src, simde__mmask16 k, simde__m512i a, simde__m256i b, const int imm8) {
|
|
#if defined(SIMDE_X86_AVX512DQ_NATIVE)
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_2_(_mm512_mask_inserti32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_epi32 ()), imm8, src, k, a, b);
|
|
return r;
|
|
#else
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_2_(simde_mm512_inserti32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_epi32 ()), imm8, a, b);
|
|
return simde_mm512_mask_mov_epi32(src, k, r);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm512_mask_inserti32x8
|
|
#define _mm512_mask_inserti32x8(src, k, a, b, imm8) simde_mm512_mask_inserti32x8(src, k, a, b, imms8)
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__m512i
|
|
simde_mm512_maskz_inserti32x8(simde__mmask16 k, simde__m512i a, simde__m256i b, const int imm8) {
|
|
#if defined(SIMDE_X86_AVX512DQ_NATIVE)
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_2_(_mm512_maskz_inserti32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_epi32 ()), imm8, k, a, b);
|
|
return r;
|
|
#else
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_2_(simde_mm512_inserti32x8, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_epi32 ()), imm8, a, b);
|
|
return simde_mm512_maskz_mov_epi32(k, r);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm512_maskz_inserti32x8
|
|
#define _mm512_maskz_inserti32x8(k, a, b, imm8) simde_mm512_maskz_inserti32x8(k, a, b, imms8)
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__m512i
|
|
simde_mm512_inserti64x2 (simde__m512i a, simde__m128i b, int imm8)
|
|
SIMDE_REQUIRE_CONSTANT_RANGE(imm8, 0, 3) {
|
|
simde__m512i_private a_ = simde__m512i_to_private(a);
|
|
|
|
a_.m128i[imm8 & 3] = b;
|
|
|
|
return simde__m512i_from_private(a_);
|
|
}
|
|
#if defined(SIMDE_X86_AVX512DQ_NATIVE)
|
|
#define simde_mm512_inserti64x2(a, b, imm8) _mm512_inserti64x2(a, b, imm8)
|
|
#endif
|
|
#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm512_inserti64x2
|
|
#define _mm512_inserti64x2(a, b, imm8) simde_mm512_inserti64x2(a, b, imm8)
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__m512i
|
|
simde_mm512_mask_inserti64x2(simde__m512i src, simde__mmask8 k, simde__m512i a, simde__m128i b, const int imm8) {
|
|
#if defined(SIMDE_X86_AVX512DQ_NATIVE)
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_4_(_mm512_mask_inserti64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, src, k, a, b);
|
|
return r;
|
|
#else
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_4_(simde_mm512_inserti64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, a, b);
|
|
return simde_mm512_mask_mov_epi64(src, k, r);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm512_mask_inserti64x2
|
|
#define _mm512_mask_inserti64x2(src, k, a, b, imm8) simde_mm512_mask_inserti64x2(src, k, a, b, imms8)
|
|
#endif
|
|
|
|
SIMDE_FUNCTION_ATTRIBUTES
|
|
simde__m512i
|
|
simde_mm512_maskz_inserti64x2(simde__mmask8 k, simde__m512i a, simde__m128i b, const int imm8) {
|
|
#if defined(SIMDE_X86_AVX512DQ_NATIVE)
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_4_(_mm512_maskz_inserti64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, k, a, b);
|
|
return r;
|
|
#else
|
|
simde__m512i r;
|
|
SIMDE_CONSTIFY_4_(simde_mm512_inserti64x2, r, (HEDLEY_UNREACHABLE(), simde_mm512_setzero_si512 ()), imm8, a, b);
|
|
return simde_mm512_maskz_mov_epi64(k, r);
|
|
#endif
|
|
}
|
|
#if defined(SIMDE_X86_AVX512DQ_ENABLE_NATIVE_ALIASES)
|
|
#undef _mm512_maskz_inserti64x2
|
|
#define _mm512_maskz_inserti64x2(k, a, b, imm8) simde_mm512_maskz_inserti64x2(k, a, b, imms8)
|
|
#endif
|
|
|
|
SIMDE_END_DECLS_
|
|
HEDLEY_DIAGNOSTIC_POP
|
|
|
|
#endif /* !defined(SIMDE_X86_AVX512_INSERT_H) */
|