jca
f6e816c4ff
Unbreak build with base gcc (no __builtin_unreachable)
2017-11-29 13:24:13 +00:00
bentley
02f05a61da
Update to verilator-3.912.
2017-10-05 08:58:51 +00:00
sthen
5e964ab0df
bump LIBCXX/LIBECXX/COMPILER_LIBCXX ports.
2017-07-26 22:45:14 +00:00
espie
c114d7057b
add pthread to COMPILER_LIBCXX.
...
white lie, but it allows clang and gcc to be more similar
bump accordingly.
2017-07-23 09:26:25 +00:00
espie
8ac47fd9c6
use COMPILER_LIBCXX where applicable
2017-07-16 19:18:47 +00:00
sthen
bcbf44ab87
use LIBCXX
2017-04-10 11:46:18 +00:00
benoit
7e8d0c3295
Update to verilator-3.900.
2017-02-13 10:27:00 +00:00
jasper
e2ffbb93ee
update to verilator-3.860
2014-05-20 19:36:27 +00:00
benoit
1d9ebbfe49
Update verilator to 3.847.
2013-05-23 15:04:41 +00:00
benoit
ce9881d3d9
- update verilator to 3.846
...
- regen PLIST
2013-05-13 11:43:24 +00:00
espie
0662a4e9d6
PERMIT_* / REGRESS->TEST sweep
2013-03-11 11:20:26 +00:00
benoit
fa4c018841
- update verilator to 3.844
...
- regen PLIST
ok jasper@
2013-01-16 07:43:48 +00:00
nigel
b4933eba88
*** empty log message ***
2011-11-17 23:33:40 +00:00
jasper
ec2bf79013
- drop a file from plist which prevented packaging...$DEITY knows where it came from
...
spotted by naddy@
2011-11-14 11:00:23 +00:00
jasper
391401eb77
import verilator-3.824
...
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.
ok aja@
2011-11-13 12:44:04 +00:00
