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import verilator-3.824

Browse Source 
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.

ok aja@
This commit is contained in:
jasper 2011-11-13 12:44:04 +00:00
parent 0f62fc2074
commit 391401eb77
4 changed files with 99 additions and 0 deletions
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30
lang/verilator/Makefile Normal file
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# $OpenBSD: Makefile,v 1.1.1.1 2011/11/13 12:44:04 jasper Exp $
COMMENT= very fast free Verilog HDL simulator
DISTNAME= verilator-3.824
CATEGORIES= lang devel
HOMEPAGE= http://www.veripool.org/wiki/verilator/Intro
# LGPLv3 or Perl
PERMIT_PACKAGE_CDROM= Yes
PERMIT_PACKAGE_FTP= Yes
PERMIT_DISTFILES_CDROM= Yes
PERMIT_DISTFILES_FTP= Yes
MASTER_SITES= http://www.veripool.org/ftp/
EXTRACT_SUFX= .tgz
WANTLIB= c m stdc++
CONFIGURE_STYLE= gnu
MAKE_FLAGS= VERILATOR_ROOT=${PREFIX}/share/verilator/ \
COPT="${CFLAGS}"
USE_GMAKE= Yes
REGRESS_TARGET= test
REGRESS_FLAGS= VERILATOR_ROOT=${WRKSRC}
.include <bsd.port.mk>

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lang/verilator/distinfo Normal file
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MD5 (verilator-3.824.tgz) = bmVYZt51NgkW4XeJOfLasQ==
RMD160 (verilator-3.824.tgz) = Q7SUJgclp60PUjV4wKxM2JThZjk=
SHA1 (verilator-3.824.tgz) = CcU12gUgWlP9kQ9MjhneeIhfiGg=
SHA256 (verilator-3.824.tgz) = KHFLIIXuhc6ULtt7V3YDsocAvV75WadlV79tu+NLKlk=
SIZE (verilator-3.824.tgz) = 1577037

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lang/verilator/pkg/DESCR Normal file
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Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.

58
lang/verilator/pkg/PLIST Normal file
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@comment $OpenBSD: PLIST,v 1.1.1.1 2011/11/13 12:44:04 jasper Exp $
bin/verilator
@bin bin/verilator_bin
@bin bin/verilator_bin_dbg
bin/verilator_profcfunc
@man man/man1/verilator.1
share/verilator/
share/verilator/bin/
share/verilator/bin/verilator_includer
share/verilator/examples/
share/verilator/examples/test_c/
share/verilator/examples/test_c/Makefile
share/verilator/examples/test_c/Makefile_obj
share/verilator/examples/test_c/sim_main.cpp
share/verilator/examples/test_c/vlt_dump.vcd
share/verilator/examples/test_sc/
share/verilator/examples/test_sc/Makefile
share/verilator/examples/test_sc/Makefile_obj
share/verilator/examples/test_sc/sc_main.cpp
share/verilator/examples/test_sp/
share/verilator/examples/test_sp/Makefile
share/verilator/examples/test_sp/Makefile_obj
share/verilator/examples/test_v/
share/verilator/examples/test_v/input.vc
share/verilator/examples/test_v/t.v
share/verilator/examples/test_v/t_chg.v
share/verilator/examples/test_v/t_clk.v
share/verilator/examples/test_v/t_clk_flop.v
share/verilator/examples/test_v/t_clk_two.v
share/verilator/examples/test_v/t_inst.v
share/verilator/examples/test_v/t_inst_a.v
share/verilator/examples/test_v/t_inst_b.v
share/verilator/examples/test_v/t_netlist.v
share/verilator/examples/test_v/t_param.v
share/verilator/examples/test_v/t_param_a.v
share/verilator/examples/test_v/t_param_b.v
share/verilator/examples/test_v/top.v
share/verilator/include/
share/verilator/include/verilated.cpp
share/verilator/include/verilated.h
share/verilator/include/verilated.mk
share/verilator/include/verilated.v
share/verilator/include/verilated_dpi.cpp
share/verilator/include/verilated_dpi.h
share/verilator/include/verilated_heavy.h
share/verilator/include/verilated_imp.h
share/verilator/include/verilated_sc.h
share/verilator/include/verilated_syms.h
share/verilator/include/verilated_vcd_c.cpp
share/verilator/include/verilated_vcd_c.h
share/verilator/include/verilated_vcd_sc.cpp
share/verilator/include/verilated_vcd_sc.h
share/verilator/include/verilated_vpi.cpp
share/verilator/include/verilated_vpi.h
share/verilator/include/verilatedos.h
share/verilator/include/vltstd/
share/verilator/include/vltstd/svdpi.h
share/verilator/include/vltstd/vpi_user.h