Public git conversion mirror of OpenBSD's official cvs ports repository. Pull requests not accepted - send diffs to the ports@ mailing list.
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Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. ok aja@ |
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README |
Documentation for the ports tree: ports(7), packages(7), mirroring-ports(7), library-specs(7), bsd.port.mk(5), port-modules(5). See also the OpenBSD Porter's Handbook http://www.openbsd.org/faq/ports/ $OpenBSD: README,v 1.19 2010/08/31 03:28:43 lum Exp $