6 Commits

Author	SHA1	Message	Date
jasper	708fc01cab	- update to iverilog 0.9.4	2011-06-13 19:42:25 +00:00
sthen	c13709faec	update DESCR; Anthony J. Bentley	2011-03-14 08:40:20 +00:00
jasper	194263d3b2	- update iverilog to 0.9.3	2010-11-17 10:16:11 +00:00
espie	88d20077a4	new depends	2010-11-17 08:05:12 +00:00
espie	88dd25abf4	USE_GROFF=Yes	2010-10-18 19:20:41 +00:00
jasper	695182bcdf	import iverilog 0.9.2 ... Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.	2010-07-08 18:58:23 +00:00