5 Commits

Author	SHA1	Message	Date
bentley	4cd0ceb6da	Update to iverilog-10.0.	2015-12-23 11:12:53 +00:00
jasper	baff6667f3	update to iverilog-0.9.7	2014-09-27 17:50:28 +00:00
bentley	71e03229ae	Update to iverilog-0.9.6. ... ok jasper@	2013-04-18 17:57:07 +00:00
sthen	c13709faec	update DESCR; Anthony J. Bentley	2011-03-14 08:40:20 +00:00
jasper	695182bcdf	import iverilog 0.9.2 ... Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.	2010-07-08 18:58:23 +00:00