some existing COMPILER lines with arch restrictions etc. In the usual
case this is now using "COMPILER = base-clang ports-gcc base-gcc" on
ports with c++ libraries in WANTLIB.
This is basically intended to be a noop on architectures using clang
as the system compiler, but help with other architectures where we
currently have many ports knocked out due to building with an unsuitable
compiler -
- some ports require c++11/newer so the GCC version in base that is used
on these archirtectures is too old.
- some ports have conflicts where an executable is built with one compiler
(e.g. gcc from base) but a library dependency is built with a different
one (e.g. gcc from ports), resulted in mixing incompatible libraries in the
same address space.
devel/gmp is intentionally skipped as it's on the path to building gcc -
the c++ library there is unused in ports (and not built by default upstream)
so intending to disable building gmpcxx in a future commit.
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.
ok aja@
