openbsd-ports/lang/verilator/Makefile

# $OpenBSD: Makefile,v 1.4 2013/03/11 11:20:29 espie Exp $

COMMENT=	very fast free Verilog HDL simulator

DISTNAME=	verilator-3.844
CATEGORIES=	lang devel

HOMEPAGE=	http://www.veripool.org/wiki/verilator/Intro

# LGPLv3 or Perl
PERMIT_PACKAGE_CDROM=	Yes

MASTER_SITES=		http://www.veripool.org/ftp/
EXTRACT_SUFX=		.tgz

WANTLIB=		c m stdc++

BUILD_DEPENDS +=	devel/bison

CONFIGURE_STYLE=	gnu
MAKE_FLAGS=		VERILATOR_ROOT=${PREFIX}/share/verilator/ \
			COPT="${CFLAGS}"

USE_GMAKE=		Yes

TEST_TARGET=		test
TEST_FLAGS=		VERILATOR_ROOT=${WRKSRC}

.include <bsd.port.mk>
PERMIT_* / REGRESS->TEST sweep 2013-03-11 07:20:26 -04:00			`# $OpenBSD: Makefile,v 1.4 2013/03/11 11:20:29 espie Exp $`
import verilator-3.824 Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. ok aja@ 2011-11-13 07:44:04 -05:00
			`COMMENT= very fast free Verilog HDL simulator`

- update verilator to 3.844 - regen PLIST ok jasper@ 2013-01-16 02:43:48 -05:00			`DISTNAME= verilator-3.844`
import verilator-3.824 Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. ok aja@ 2011-11-13 07:44:04 -05:00			`CATEGORIES= lang devel`

			`HOMEPAGE= http://www.veripool.org/wiki/verilator/Intro`

			`# LGPLv3 or Perl`
			`PERMIT_PACKAGE_CDROM= Yes`

			`MASTER_SITES= http://www.veripool.org/ftp/`
			`EXTRACT_SUFX= .tgz`

			`WANTLIB= c m stdc++`

* empty log message * 2011-11-17 18:33:40 -05:00			`BUILD_DEPENDS += devel/bison`

import verilator-3.824 Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. ok aja@ 2011-11-13 07:44:04 -05:00			`CONFIGURE_STYLE= gnu`
			`MAKE_FLAGS= VERILATOR_ROOT=${PREFIX}/share/verilator/ \`
			`COPT="${CFLAGS}"`

			`USE_GMAKE= Yes`

PERMIT_* / REGRESS->TEST sweep 2013-03-11 07:20:26 -04:00			`TEST_TARGET= test`
			`TEST_FLAGS= VERILATOR_ROOT=${WRKSRC}`
import verilator-3.824 Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. ok aja@ 2011-11-13 07:44:04 -05:00
* empty log message * 2011-11-17 18:33:40 -05:00			`.include <bsd.port.mk>`