2010-07-08 14:58:23 -04:00
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates
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as a compiler, compiling source code writen in Verilog (IEEE-1364) into
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2011-03-14 04:40:20 -04:00
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some target format. For batch simulation, the compiler can generate an
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intermediate form called vvp assembly. This intermediate form is
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executed by the "vvp" command. For synthesis, the compiler generates
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netlists in the desired format.
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2010-07-08 14:58:23 -04:00
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The compiler proper is intended to parse and elaborate design
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2011-03-14 04:40:20 -04:00
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descriptions written to the IEEE standard IEEE Std 1364-2005. This is a
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fairly large and complex standard, so it will take some time for it to
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get there, but that's the goal.
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