188 lines
4.6 KiB
C
188 lines
4.6 KiB
C
/* startup.crc.c -- entry point at reset and C startup
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** Copyright (c) 2020-2021 Renaud Fivet
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** v8: flash CRC32 validation
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** v7: isr vector mapped to RAM to enable in RAM execution
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** v6: device specific interrupts mapped
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** v5: System Exceptions mapped
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** v4: calls to init() and main()
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** v3: data and bss RAM memory initialization
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** v2: SysTick System Exception mapped
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** v1: stack and entry point
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*/
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#include "system.h" /* init() */
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#include "stm32f030xx.h"
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/* Memory locations defined by linker script */
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void __StackTop( void) ; /* __StackTop points after end of stack */
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void Reset_Handler( void) ; /* Entry point for execution */
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extern const long __etext[] ; /* start of initialized data copy in flash */
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extern long __data_start__[] ;
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extern long __bss_start__[] ;
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extern long __bss_end__ ; /* &__bss_end__ points after end of bss */
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/* Stubs for System Exception Handler */
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void Default_Handler( void) ;
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#define dflt_hndlr( fun) void fun##_Handler( void) \
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__attribute__((weak,alias("Default_Handler")))
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dflt_hndlr( NMI) ;
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dflt_hndlr( HardFault) ;
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dflt_hndlr( SVCall) ;
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dflt_hndlr( PendSV) ;
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dflt_hndlr( SysTick) ;
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dflt_hndlr( WWDG) ;
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dflt_hndlr( RTC) ;
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dflt_hndlr( FLASH) ;
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dflt_hndlr( RCC) ;
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dflt_hndlr( EXTI0_1) ;
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dflt_hndlr( EXTI2_3) ;
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dflt_hndlr( EXTI4_15) ;
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dflt_hndlr( DMA_CH1) ;
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dflt_hndlr( DMA_CH2_3) ;
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dflt_hndlr( DMA_CH4_5) ;
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dflt_hndlr( ADC) ;
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dflt_hndlr( TIM1_BRK_UP_TRG_COM) ;
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dflt_hndlr( TIM1_CC) ;
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dflt_hndlr( TIM3) ;
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dflt_hndlr( TIM6) ;
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dflt_hndlr( TIM14) ;
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dflt_hndlr( TIM15) ;
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dflt_hndlr( TIM16) ;
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dflt_hndlr( TIM17) ;
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dflt_hndlr( I2C1) ;
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dflt_hndlr( I2C2) ;
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dflt_hndlr( SPI1) ;
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dflt_hndlr( SPI2) ;
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dflt_hndlr( USART1) ;
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dflt_hndlr( USART2) ;
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dflt_hndlr( USART3_4_5_6) ;
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dflt_hndlr( USB) ;
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/* Interrupt vector table:
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* 1 Stack Pointer reset value
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* 15 System Exceptions
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* 32 Device specific Interrupts
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*/
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typedef void (*isr_p)( void) ;
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isr_p const isr_vector[ 16 + 32] __attribute__((section(".isr_vector"))) = {
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__StackTop,
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/* System Exceptions */
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Reset_Handler,
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NMI_Handler,
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HardFault_Handler,
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0, 0, 0, 0, 0, 0, 0,
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SVCall_Handler,
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0, 0,
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PendSV_Handler,
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SysTick_Handler,
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/* STM32F030xx specific Interrupts cf RM0360 */
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WWDG_Handler,
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0,
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RTC_Handler,
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FLASH_Handler,
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RCC_Handler,
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EXTI0_1_Handler,
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EXTI2_3_Handler,
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EXTI4_15_Handler,
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0,
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DMA_CH1_Handler,
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DMA_CH2_3_Handler,
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DMA_CH4_5_Handler,
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ADC_Handler,
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TIM1_BRK_UP_TRG_COM_Handler,
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TIM1_CC_Handler,
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0,
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TIM3_Handler,
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TIM6_Handler,
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0,
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TIM14_Handler,
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TIM15_Handler,
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TIM16_Handler,
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TIM17_Handler,
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I2C1_Handler,
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I2C2_Handler,
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SPI1_Handler,
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SPI2_Handler,
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USART1_Handler,
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USART2_Handler,
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USART3_4_5_6_Handler,
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0,
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USB_Handler
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} ;
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#if RAMISRV == 2
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# define ISRV_SIZE (sizeof isr_vector / sizeof *isr_vector)
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isr_p ram_vector[ ISRV_SIZE] __attribute__((section(".ram_vector"))) ;
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#endif
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int main( void) ;
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#ifdef CRC32SIGN
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const unsigned crcsum __attribute__((section(".crc_chk"))) = 0xDEC0ADDE ;
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static int check_flash( void) {
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int ret = 0 ;
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/* Flash CRC validation */
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RCC_AHBENR |= RCC_AHBENR_CRCEN ; /* Enable CRC periph */
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CRC_CR = 1 ; /* Reset */
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if( CRC_DR == 0xFFFFFFFF) { /* CRC periph is alive and resetted */
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const unsigned *wp = (const unsigned *) isr_vector ;
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while( wp <= &crcsum)
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CRC_DR = *wp++ ;
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ret = CRC_DR == 0 ;
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}
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RCC_AHBENR &= ~RCC_AHBENR_CRCEN ; /* Disable CRC periph */
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return ret ;
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}
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#endif
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void Reset_Handler( void) {
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const long *f ; /* from, source constant data from FLASH */
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long *t ; /* to, destination in RAM */
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#if RAMISRV == 2
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/* Copy isr vector to beginning of RAM */
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for( unsigned i = 0 ; i < ISRV_SIZE ; i++)
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ram_vector[ i] = isr_vector[ i] ;
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#endif
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/* Assume:
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** __bss_start__ == __data_end__
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** All sections are 4 bytes aligned
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*/
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f = __etext ;
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for( t = __data_start__ ; t < __bss_start__ ; t += 1)
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*t = *f++ ;
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while( t < &__bss_end__)
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*t++ = 0 ;
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/* Make sure active isr vector is mapped at 0x0 before enabling interrupts */
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RCC_APB2ENR |= RCC_APB2ENR_SYSCFGEN ; /* Enable SYSCFG */
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#if RAMISRV
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SYSCFG_CFGR1 |= 3 ; /* Map RAM at 0x0 */
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#else
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SYSCFG_CFGR1 &= ~3 ; /* Map FLASH at 0x0 */
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#endif
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if(
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#ifdef CRC32SIGN
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check_flash() &&
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#endif
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init() == 0)
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main() ;
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for( ;;)
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__asm( "WFI") ; /* Wait for interrupt */
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}
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void Default_Handler( void) {
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for( ;;) ;
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}
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/* end of startup.crc.c */
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