mirror of
https://github.com/rfivet/stm32bringup.git
synced 2024-12-18 06:46:23 -05:00
CRC32 validation of binary image at startup.
This commit is contained in:
parent
d13ec1241c
commit
5d090f6944
41
Makefile
41
Makefile
@ -42,6 +42,7 @@ SIZE = $(BINPFX)size
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PROJECT = f030f4
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PROJECT = f030f4
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### Memory Models
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### Memory Models
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# By default we use the memory mapping from linker script
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# In RAM Execution, load and start by USART bootloader
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# In RAM Execution, load and start by USART bootloader
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# Bootloader uses first 2K of RAM, execution from bootloader
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# Bootloader uses first 2K of RAM, execution from bootloader
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@ -59,12 +60,12 @@ PROJECT = f030f4
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# In Flash Execution
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# In Flash Execution
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# if FLASHSTART is not at beginning of FLASH: execution via bootloader or SWD
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# if FLASHSTART is not at beginning of FLASH: execution via bootloader or SWD
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FLASHSTART = 0x08000000
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#FLASHSTART = 0x08000000
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FLASHSIZE = 16K
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#FLASHSIZE = 16K
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RAMSTART = 0x20000000
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#RAMSTART = 0x20000000
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RAMSIZE = 4K
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#RAMSIZE = 4K
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# ISR vector copied and mapped to RAM if FLASHSTART != 0x08000000
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# ISR vector copied and mapped to RAM when FLASHSTART != 0x08000000
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ifdef FLASHSTART
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ifdef FLASHSTART
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ifneq ($(FLASHSTART),0x08000000)
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ifneq ($(FLASHSTART),0x08000000)
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ifeq ($(FLASHSTART),0x20000000)
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ifeq ($(FLASHSTART),0x20000000)
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@ -75,9 +76,15 @@ ifdef FLASHSTART
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RAMISRV := 2
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RAMISRV := 2
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endif
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endif
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endif
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endif
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FNAMLOC = .$(FLASHSTART)
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BINLOC = $(FLASHSTART)
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else
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BINLOC = 0x08000000
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endif
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endif
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# build options
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CRC32SIGN := 1
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#SRCS = boot.c
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#SRCS = boot.c
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#SRCS = ledon.c
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#SRCS = ledon.c
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#SRCS = blink.c
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#SRCS = blink.c
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@ -96,7 +103,8 @@ endif
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#SRCS = startup.txeie.c gpioa.c ds18b20main.c ds18b20.c
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#SRCS = startup.txeie.c gpioa.c ds18b20main.c ds18b20.c
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#SRCS = startup.txeie.c adc.c adcmain.c
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#SRCS = startup.txeie.c adc.c adcmain.c
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#SRCS = startup.txeie.c adc.c adccalib.c ds18b20.c
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#SRCS = startup.txeie.c adc.c adccalib.c ds18b20.c
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SRCS = startup.ram.c txeie.c uptime.1.c
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#SRCS = startup.ram.c txeie.c uptime.1.c
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SRCS = startup.crc.c txeie.c uptime.1.c
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OBJS = $(SRCS:.c=.o)
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OBJS = $(SRCS:.c=.o)
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LIBOBJS = printf.o putchar.o puts.o memset.o memcpy.o
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LIBOBJS = printf.o putchar.o puts.o memset.o memcpy.o
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@ -104,7 +112,10 @@ CPU = -mthumb -mcpu=cortex-m0
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ifdef RAMISRV
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ifdef RAMISRV
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CDEFINES = -DRAMISRV=$(RAMISRV)
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CDEFINES = -DRAMISRV=$(RAMISRV)
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endif
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endif
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WARNINGS=-pedantic -Wall -Wextra -Wstrict-prototypes -Wno-unused-parameter
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ifdef CRC32SIGN
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CDEFINES += -DCRC32SIGN=$(CRC32SIGN)
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endif
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WARNINGS=-pedantic -Wall -Wextra -Wstrict-prototypes
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CFLAGS = $(CPU) -g $(WARNINGS) -Os $(CDEFINES)
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CFLAGS = $(CPU) -g $(WARNINGS) -Os $(CDEFINES)
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LD_SCRIPT = generic.ld
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LD_SCRIPT = generic.ld
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@ -121,7 +132,7 @@ LDFLAGS =-Wl,$(subst $(space),$(comma),$(LDOPTS))
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.PHONY: clean all version
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.PHONY: clean all version
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all: $(PROJECT).hex $(PROJECT)$(FNAMLOC).bin
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all: $(PROJECT).$(BINLOC).bin $(PROJECT).hex
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version:
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version:
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@echo make $(MAKE_VERSION) $(MAKE_HOST)
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@echo make $(MAKE_VERSION) $(MAKE_HOST)
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@ -145,15 +156,21 @@ cstartup.elf: cstartup.o
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$(SIZE) -G $@
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$(SIZE) -G $@
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$(OBJDUMP) -hS $@ > $(subst .elf,.lst,$@)
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$(OBJDUMP) -hS $@ > $(subst .elf,.lst,$@)
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ifdef FNAMLOC
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%.bin: %.elf
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%.bin: %.elf
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@echo $@
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@echo $@
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$(OBJCOPY) -O binary $< $@
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$(OBJCOPY) -O binary $< $@
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endif
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%$(FNAMLOC).bin: %.elf
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%.$(BINLOC).bin: %.elf
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@echo $@
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@echo $@
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$(OBJCOPY) -O binary $< $@
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$(OBJCOPY) -O binary $< $@
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ifdef CRC32SIGN
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crc32/sign32 $@
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mv signed.bin $@
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%.hex: %.$(BINLOC).bin
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@echo $@
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$(OBJCOPY) --change-address=$(BINLOC) -I binary -O ihex $< $@
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endif
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%.hex: %.elf
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%.hex: %.elf
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@echo $@
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@echo $@
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8
crc32/Makefile
Normal file
8
crc32/Makefile
Normal file
@ -0,0 +1,8 @@
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# Makefile -- sign32
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# Copyright (c) 2021 Renaud Fivet
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# silence unused parameter warning
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WARNINGS=-pedantic -Wall -Wextra -Wstrict-prototypes -Wno-unused-parameter
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CFLAGS = $(WARNINGS) -O2
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all: sign32
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228
crc32/sign32.c
Normal file
228
crc32/sign32.c
Normal file
@ -0,0 +1,228 @@
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/* sign32.c -- sign a binary file with crc32 checksum */
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/* Copyright (c) 2021 Renaud Fivet */
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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/*
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** POLY32 is 0x04C11DB7
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** Intialisation 0xFFFFFFFF
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** High bit first (left shift)
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** 32 bit word input, little endian
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** crc = CRC32( crc, word)
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** CRC32( 0xFFFFFFFF, 0xFFFFFFFF) == 0
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** CRC32( 0, 0) == 0
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** CRC32( 0xFFFFFFFF, 0x00000000) == -955982469, 0xC704DD7B
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*/
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/*
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** define BITWISE if you want calculation made by bit otherwise by byte
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** when BITWISE, define UNROLL to speed up things a bit
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** define GENTABLE to printout bytewise calculation table
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**
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** GENTABLE + BITWISE print bytewise table using bitwise calculation
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** GENTABLE + BITWISE + UNROLL print bytewise table using unrolled bitwise table calculation
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** GENTABLE print bytewise table using bytewise table calculation
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** BITWISE binary sign using bitwise calculation
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** BITWISE + UNROLL binary sign using unrolled bitwise table calculation
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** nothing defined binary sign using bytewise table calculation
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*/
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#ifdef BITWISE
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#define POLY32 0x04C11DB7
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static uint32_t crc32( uint32_t crc, unsigned char c) {
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#ifndef UNROLL
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int i ;
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crc ^= c << 24 ;
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for( i = 8 ; i ; i--) {
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if( crc & 0x80000000)
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crc = (crc << 1) ^ POLY32 ;
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else
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crc <<= 1 ;
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}
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#else
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static const uint32_t crc32tab[ 2] = { 0, POLY32 } ;
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crc ^= (c << 24) ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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crc = (crc << 1) ^ crc32tab[ (crc & 0x80000000) != 0] ;
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#endif
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return crc ;
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}
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#else
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#define crc32( crc, c) crc32tab[ (crc >> 24) ^ c] ^ (crc << 8)
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static const uint32_t crc32tab[ 256] = {
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0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9,
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0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005,
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0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61,
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0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD,
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0x4C11DB70, 0x48D0C6C7, 0x4593E01E, 0x4152FDA9,
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0x5F15ADAC, 0x5BD4B01B, 0x569796C2, 0x52568B75,
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0x6A1936C8, 0x6ED82B7F, 0x639B0DA6, 0x675A1011,
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0x791D4014, 0x7DDC5DA3, 0x709F7B7A, 0x745E66CD,
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0x9823B6E0, 0x9CE2AB57, 0x91A18D8E, 0x95609039,
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0x8B27C03C, 0x8FE6DD8B, 0x82A5FB52, 0x8664E6E5,
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0xBE2B5B58, 0xBAEA46EF, 0xB7A96036, 0xB3687D81,
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0xAD2F2D84, 0xA9EE3033, 0xA4AD16EA, 0xA06C0B5D,
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0xD4326D90, 0xD0F37027, 0xDDB056FE, 0xD9714B49,
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0xC7361B4C, 0xC3F706FB, 0xCEB42022, 0xCA753D95,
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0xF23A8028, 0xF6FB9D9F, 0xFBB8BB46, 0xFF79A6F1,
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0xE13EF6F4, 0xE5FFEB43, 0xE8BCCD9A, 0xEC7DD02D,
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0x34867077, 0x30476DC0, 0x3D044B19, 0x39C556AE,
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0x278206AB, 0x23431B1C, 0x2E003DC5, 0x2AC12072,
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0x128E9DCF, 0x164F8078, 0x1B0CA6A1, 0x1FCDBB16,
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0x018AEB13, 0x054BF6A4, 0x0808D07D, 0x0CC9CDCA,
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0x7897AB07, 0x7C56B6B0, 0x71159069, 0x75D48DDE,
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0x6B93DDDB, 0x6F52C06C, 0x6211E6B5, 0x66D0FB02,
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0x5E9F46BF, 0x5A5E5B08, 0x571D7DD1, 0x53DC6066,
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0x4D9B3063, 0x495A2DD4, 0x44190B0D, 0x40D816BA,
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0xACA5C697, 0xA864DB20, 0xA527FDF9, 0xA1E6E04E,
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0xBFA1B04B, 0xBB60ADFC, 0xB6238B25, 0xB2E29692,
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0x8AAD2B2F, 0x8E6C3698, 0x832F1041, 0x87EE0DF6,
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0x99A95DF3, 0x9D684044, 0x902B669D, 0x94EA7B2A,
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0xE0B41DE7, 0xE4750050, 0xE9362689, 0xEDF73B3E,
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0xF3B06B3B, 0xF771768C, 0xFA325055, 0xFEF34DE2,
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0xC6BCF05F, 0xC27DEDE8, 0xCF3ECB31, 0xCBFFD686,
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0xD5B88683, 0xD1799B34, 0xDC3ABDED, 0xD8FBA05A,
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0x690CE0EE, 0x6DCDFD59, 0x608EDB80, 0x644FC637,
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0x7A089632, 0x7EC98B85, 0x738AAD5C, 0x774BB0EB,
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0x4F040D56, 0x4BC510E1, 0x46863638, 0x42472B8F,
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0x5C007B8A, 0x58C1663D, 0x558240E4, 0x51435D53,
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0x251D3B9E, 0x21DC2629, 0x2C9F00F0, 0x285E1D47,
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0x36194D42, 0x32D850F5, 0x3F9B762C, 0x3B5A6B9B,
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0x0315D626, 0x07D4CB91, 0x0A97ED48, 0x0E56F0FF,
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0x1011A0FA, 0x14D0BD4D, 0x19939B94, 0x1D528623,
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0xF12F560E, 0xF5EE4BB9, 0xF8AD6D60, 0xFC6C70D7,
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0xE22B20D2, 0xE6EA3D65, 0xEBA91BBC, 0xEF68060B,
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0xD727BBB6, 0xD3E6A601, 0xDEA580D8, 0xDA649D6F,
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0xC423CD6A, 0xC0E2D0DD, 0xCDA1F604, 0xC960EBB3,
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0xBD3E8D7E, 0xB9FF90C9, 0xB4BCB610, 0xB07DABA7,
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0xAE3AFBA2, 0xAAFBE615, 0xA7B8C0CC, 0xA379DD7B,
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0x9B3660C6, 0x9FF77D71, 0x92B45BA8, 0x9675461F,
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0x8832161A, 0x8CF30BAD, 0x81B02D74, 0x857130C3,
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0x5D8A9099, 0x594B8D2E, 0x5408ABF7, 0x50C9B640,
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0x4E8EE645, 0x4A4FFBF2, 0x470CDD2B, 0x43CDC09C,
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0x7B827D21, 0x7F436096, 0x7200464F, 0x76C15BF8,
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0x68860BFD, 0x6C47164A, 0x61043093, 0x65C52D24,
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0x119B4BE9, 0x155A565E, 0x18197087, 0x1CD86D30,
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0x029F3D35, 0x065E2082, 0x0B1D065B, 0x0FDC1BEC,
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0x3793A651, 0x3352BBE6, 0x3E119D3F, 0x3AD08088,
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0x2497D08D, 0x2056CD3A, 0x2D15EBE3, 0x29D4F654,
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0xC5A92679, 0xC1683BCE, 0xCC2B1D17, 0xC8EA00A0,
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0xD6AD50A5, 0xD26C4D12, 0xDF2F6BCB, 0xDBEE767C,
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0xE3A1CBC1, 0xE760D676, 0xEA23F0AF, 0xEEE2ED18,
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0xF0A5BD1D, 0xF464A0AA, 0xF9278673, 0xFDE69BC4,
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0x89B8FD09, 0x8D79E0BE, 0x803AC667, 0x84FBDBD0,
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0x9ABC8BD5, 0x9E7D9662, 0x933EB0BB, 0x97FFAD0C,
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0xAFB010B1, 0xAB710D06, 0xA6322BDF, 0xA2F33668,
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0xBCB4666D, 0xB8757BDA, 0xB5365D03, 0xB1F740B4
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} ;
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#endif
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#ifdef GENTABLE
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static void print_table( void) {
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#define TABSIZE 256
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int i ;
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printf( "const uint32_t crc32tab[ %i] = {\n ", TABSIZE) ;
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for( i = 0 ; i < TABSIZE ; i++)
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printf( "0x%08X,%s", crc32( 0, i), !((i + 1) % 4) ? "\n " : " ") ;
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printf( "\n} ;\n") ;
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}
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int main() {
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print_table() ;
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return EXIT_SUCCESS ;
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}
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#else
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static uint32_t check_word( uint32_t crc, unsigned char buf[ 4]) {
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crc = crc32( crc, buf[ 3]) ;
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crc = crc32( crc, buf[ 2]) ;
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crc = crc32( crc, buf[ 1]) ;
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crc = crc32( crc, buf[ 0]) ;
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return crc ;
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}
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int sign_file( char *filename) {
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FILE *fin, *fout ;
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int cnt, filesize, outsize ;
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uint32_t crc ;
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unsigned char buf[ 4] ;
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const char outname[] = "signed.bin" ;
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fin = fopen( filename, "rb") ;
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if( !fin) {
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perror( filename) ;
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return EXIT_FAILURE ;
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}
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fout = fopen( outname, "wb") ;
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if( !fout) {
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perror( outname) ;
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fclose( fin) ;
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return EXIT_FAILURE ;
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}
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||||||
|
|
||||||
|
crc = 0xFFFFFFFF ;
|
||||||
|
filesize = 0 ;
|
||||||
|
while( !feof( fin)) {
|
||||||
|
cnt = fread( buf, 1, sizeof buf, fin) ;
|
||||||
|
if( *((unsigned *) buf) == 0xDEC0ADDE) /* DEADC0DE Placeholder */
|
||||||
|
break ;
|
||||||
|
|
||||||
|
filesize += cnt ;
|
||||||
|
if( cnt != 4) {
|
||||||
|
if( cnt == 0)
|
||||||
|
break ;
|
||||||
|
|
||||||
|
while( cnt < 4) /* pad with zeroes */
|
||||||
|
buf[ cnt++] = 0 ;
|
||||||
|
}
|
||||||
|
|
||||||
|
crc = check_word( crc, buf) ;
|
||||||
|
fwrite( buf, 1, 4, fout) ;
|
||||||
|
}
|
||||||
|
|
||||||
|
outsize = (filesize + 3) & ~3 ;
|
||||||
|
if( crc) { /* Sign only if input was not signed already */
|
||||||
|
fwrite( &crc, 1, 4, fout) ;
|
||||||
|
outsize += 4 ;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf( "%08X %s: %i, %s: %i\n", crc, filename, filesize, outname, outsize) ;
|
||||||
|
fclose( fout) ;
|
||||||
|
fclose( fin) ;
|
||||||
|
return EXIT_SUCCESS ;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int main( int argc, char *argv[]) {
|
||||||
|
int ret = EXIT_SUCCESS ;
|
||||||
|
|
||||||
|
while( (ret == EXIT_SUCCESS) && *++argv)
|
||||||
|
ret = sign_file( *argv) ;
|
||||||
|
|
||||||
|
return ret ;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* end of sign32.c */
|
||||||
@ -1,5 +1,5 @@
|
|||||||
/* generic.ld -- parametrized linker script */
|
/* generic.ld -- parameterized linker script */
|
||||||
/* Copyright (c) 2021 Renaud Fivet */
|
/* Copyright (c) 2021 Renaud Fivet */
|
||||||
|
|
||||||
/* Linker script to configure memory regions.
|
/* Linker script to configure memory regions.
|
||||||
* Need modifying for a specific board.
|
* Need modifying for a specific board.
|
||||||
@ -195,6 +195,11 @@ SECTIONS
|
|||||||
*(.stack*)
|
*(.stack*)
|
||||||
} > RAM
|
} > RAM
|
||||||
|
|
||||||
|
.crc : AT (__etext + (__data_end__ - __data_start__))
|
||||||
|
{
|
||||||
|
KEEP(*(.crc_chk))
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
/* Set stack top to end of RAM, and stack limit move down by
|
/* Set stack top to end of RAM, and stack limit move down by
|
||||||
* size of stack_dummy section */
|
* size of stack_dummy section */
|
||||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||||
|
|||||||
187
startup.crc.c
Normal file
187
startup.crc.c
Normal file
@ -0,0 +1,187 @@
|
|||||||
|
/* startup.crc.c -- entry point at reset and C startup
|
||||||
|
** Copyright (c) 2020-2021 Renaud Fivet
|
||||||
|
** v8: flash CRC32 validation
|
||||||
|
** v7: isr vector mapped to RAM to enable in RAM execution
|
||||||
|
** v6: device specific interrupts mapped
|
||||||
|
** v5: System Exceptions mapped
|
||||||
|
** v4: calls to init() and main()
|
||||||
|
** v3: data and bss RAM memory initialization
|
||||||
|
** v2: SysTick System Exception mapped
|
||||||
|
** v1: stack and entry point
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "system.h" /* init() */
|
||||||
|
#include "stm32f030xx.h"
|
||||||
|
|
||||||
|
/* Memory locations defined by linker script */
|
||||||
|
void __StackTop( void) ; /* __StackTop points after end of stack */
|
||||||
|
void Reset_Handler( void) ; /* Entry point for execution */
|
||||||
|
extern const long __etext[] ; /* start of initialized data copy in flash */
|
||||||
|
extern long __data_start__[] ;
|
||||||
|
extern long __bss_start__[] ;
|
||||||
|
extern long __bss_end__ ; /* &__bss_end__ points after end of bss */
|
||||||
|
|
||||||
|
/* Stubs for System Exception Handler */
|
||||||
|
void Default_Handler( void) ;
|
||||||
|
#define dflt_hndlr( fun) void fun##_Handler( void) \
|
||||||
|
__attribute__((weak,alias("Default_Handler")))
|
||||||
|
dflt_hndlr( NMI) ;
|
||||||
|
dflt_hndlr( HardFault) ;
|
||||||
|
dflt_hndlr( SVCall) ;
|
||||||
|
dflt_hndlr( PendSV) ;
|
||||||
|
dflt_hndlr( SysTick) ;
|
||||||
|
|
||||||
|
dflt_hndlr( WWDG) ;
|
||||||
|
dflt_hndlr( RTC) ;
|
||||||
|
dflt_hndlr( FLASH) ;
|
||||||
|
dflt_hndlr( RCC) ;
|
||||||
|
dflt_hndlr( EXTI0_1) ;
|
||||||
|
dflt_hndlr( EXTI2_3) ;
|
||||||
|
dflt_hndlr( EXTI4_15) ;
|
||||||
|
dflt_hndlr( DMA_CH1) ;
|
||||||
|
dflt_hndlr( DMA_CH2_3) ;
|
||||||
|
dflt_hndlr( DMA_CH4_5) ;
|
||||||
|
dflt_hndlr( ADC) ;
|
||||||
|
dflt_hndlr( TIM1_BRK_UP_TRG_COM) ;
|
||||||
|
dflt_hndlr( TIM1_CC) ;
|
||||||
|
dflt_hndlr( TIM3) ;
|
||||||
|
dflt_hndlr( TIM6) ;
|
||||||
|
dflt_hndlr( TIM14) ;
|
||||||
|
dflt_hndlr( TIM15) ;
|
||||||
|
dflt_hndlr( TIM16) ;
|
||||||
|
dflt_hndlr( TIM17) ;
|
||||||
|
dflt_hndlr( I2C1) ;
|
||||||
|
dflt_hndlr( I2C2) ;
|
||||||
|
dflt_hndlr( SPI1) ;
|
||||||
|
dflt_hndlr( SPI2) ;
|
||||||
|
dflt_hndlr( USART1) ;
|
||||||
|
dflt_hndlr( USART2) ;
|
||||||
|
dflt_hndlr( USART3_4_5_6) ;
|
||||||
|
dflt_hndlr( USB) ;
|
||||||
|
|
||||||
|
/* Interrupt vector table:
|
||||||
|
* 1 Stack Pointer reset value
|
||||||
|
* 15 System Exceptions
|
||||||
|
* 32 Device specific Interrupts
|
||||||
|
*/
|
||||||
|
typedef void (*isr_p)( void) ;
|
||||||
|
isr_p const isr_vector[ 16 + 32] __attribute__((section(".isr_vector"))) = {
|
||||||
|
__StackTop,
|
||||||
|
/* System Exceptions */
|
||||||
|
Reset_Handler,
|
||||||
|
NMI_Handler,
|
||||||
|
HardFault_Handler,
|
||||||
|
0, 0, 0, 0, 0, 0, 0,
|
||||||
|
SVCall_Handler,
|
||||||
|
0, 0,
|
||||||
|
PendSV_Handler,
|
||||||
|
SysTick_Handler,
|
||||||
|
/* STM32F030xx specific Interrupts cf RM0360 */
|
||||||
|
WWDG_Handler,
|
||||||
|
0,
|
||||||
|
RTC_Handler,
|
||||||
|
FLASH_Handler,
|
||||||
|
RCC_Handler,
|
||||||
|
EXTI0_1_Handler,
|
||||||
|
EXTI2_3_Handler,
|
||||||
|
EXTI4_15_Handler,
|
||||||
|
0,
|
||||||
|
DMA_CH1_Handler,
|
||||||
|
DMA_CH2_3_Handler,
|
||||||
|
DMA_CH4_5_Handler,
|
||||||
|
ADC_Handler,
|
||||||
|
TIM1_BRK_UP_TRG_COM_Handler,
|
||||||
|
TIM1_CC_Handler,
|
||||||
|
0,
|
||||||
|
TIM3_Handler,
|
||||||
|
TIM6_Handler,
|
||||||
|
0,
|
||||||
|
TIM14_Handler,
|
||||||
|
TIM15_Handler,
|
||||||
|
TIM16_Handler,
|
||||||
|
TIM17_Handler,
|
||||||
|
I2C1_Handler,
|
||||||
|
I2C2_Handler,
|
||||||
|
SPI1_Handler,
|
||||||
|
SPI2_Handler,
|
||||||
|
USART1_Handler,
|
||||||
|
USART2_Handler,
|
||||||
|
USART3_4_5_6_Handler,
|
||||||
|
0,
|
||||||
|
USB_Handler
|
||||||
|
} ;
|
||||||
|
|
||||||
|
#if RAMISRV == 2
|
||||||
|
# define ISRV_SIZE (sizeof isr_vector / sizeof *isr_vector)
|
||||||
|
isr_p ram_vector[ ISRV_SIZE] __attribute__((section(".ram_vector"))) ;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int main( void) ;
|
||||||
|
|
||||||
|
#ifdef CRC32SIGN
|
||||||
|
const unsigned crcsum __attribute__((section(".crc_chk"))) = 0xDEC0ADDE ;
|
||||||
|
|
||||||
|
static int check_flash( void) {
|
||||||
|
int ret = 0 ;
|
||||||
|
|
||||||
|
/* Flash CRC validation */
|
||||||
|
RCC_AHBENR |= RCC_AHBENR_CRCEN ; /* Enable CRC periph */
|
||||||
|
CRC_CR = 1 ; /* Reset */
|
||||||
|
if( CRC_DR == 0xFFFFFFFF) { /* CRC periph is alive and resetted */
|
||||||
|
const unsigned *wp = (const unsigned *) isr_vector ;
|
||||||
|
while( wp <= &crcsum)
|
||||||
|
CRC_DR = *wp++ ;
|
||||||
|
|
||||||
|
ret = CRC_DR == 0 ;
|
||||||
|
}
|
||||||
|
|
||||||
|
RCC_AHBENR &= ~RCC_AHBENR_CRCEN ; /* Disable CRC periph */
|
||||||
|
return ret ;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void Reset_Handler( void) {
|
||||||
|
const long *f ; /* from, source constant data from FLASH */
|
||||||
|
long *t ; /* to, destination in RAM */
|
||||||
|
|
||||||
|
#if RAMISRV == 2
|
||||||
|
/* Copy isr vector to beginning of RAM */
|
||||||
|
for( unsigned i = 0 ; i < ISRV_SIZE ; i++)
|
||||||
|
ram_vector[ i] = isr_vector[ i] ;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Assume:
|
||||||
|
** __bss_start__ == __data_end__
|
||||||
|
** All sections are 4 bytes aligned
|
||||||
|
*/
|
||||||
|
f = __etext ;
|
||||||
|
for( t = __data_start__ ; t < __bss_start__ ; t += 1)
|
||||||
|
*t = *f++ ;
|
||||||
|
|
||||||
|
while( t < &__bss_end__)
|
||||||
|
*t++ = 0 ;
|
||||||
|
|
||||||
|
/* Make sure active isr vector is mapped at 0x0 before enabling interrupts */
|
||||||
|
RCC_APB2ENR |= RCC_APB2ENR_SYSCFGEN ; /* Enable SYSCFG */
|
||||||
|
#if RAMISRV
|
||||||
|
SYSCFG_CFGR1 |= 3 ; /* Map RAM at 0x0 */
|
||||||
|
#else
|
||||||
|
SYSCFG_CFGR1 &= ~3 ; /* Map FLASH at 0x0 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if(
|
||||||
|
#ifdef CRC32SIGN
|
||||||
|
check_flash() &&
|
||||||
|
#endif
|
||||||
|
init() == 0)
|
||||||
|
main() ;
|
||||||
|
|
||||||
|
for( ;;)
|
||||||
|
__asm( "WFI") ; /* Wait for interrupt */
|
||||||
|
}
|
||||||
|
|
||||||
|
void Default_Handler( void) {
|
||||||
|
for( ;;) ;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* end of startup.crc.c */
|
||||||
@ -39,10 +39,11 @@
|
|||||||
#define RCC_CFGR_PLLXTPRE 0x00020000
|
#define RCC_CFGR_PLLXTPRE 0x00020000
|
||||||
#define RCC_CFGR_PLLXTPRE_DIV1 0x00000000 /* HSE */
|
#define RCC_CFGR_PLLXTPRE_DIV1 0x00000000 /* HSE */
|
||||||
#define RCC_CFGR_PLLXTPRE_DIV2 0x00020000 /* HSE / 2 */
|
#define RCC_CFGR_PLLXTPRE_DIV2 0x00020000 /* HSE / 2 */
|
||||||
#define RCC_CFGR_PLLMUL_MSK (0x00F << 18)
|
#define RCC_CFGR_PLLMUL_MSK (0x0F << 18)
|
||||||
#define RCC_CFGR_PLLMUL( v) ((v - 2) << 18)
|
#define RCC_CFGR_PLLMUL( v) ((v - 2) << 18)
|
||||||
|
|
||||||
#define RCC_AHBENR RCC[ 5]
|
#define RCC_AHBENR RCC[ 5]
|
||||||
|
#define RCC_AHBENR_CRCEN (1 << 6) /* 6: CRC clock enable */
|
||||||
#define RCC_AHBENR_IOPn( n) (1 << (17 + n))
|
#define RCC_AHBENR_IOPn( n) (1 << (17 + n))
|
||||||
#define RCC_AHBENR_IOPh( h) RCC_AHBENR_IOPn( CAT( 0x, h) - 0xA)
|
#define RCC_AHBENR_IOPh( h) RCC_AHBENR_IOPn( CAT( 0x, h) - 0xA)
|
||||||
|
|
||||||
@ -56,6 +57,13 @@
|
|||||||
#define RCC_CR2_HSI14RDY 0x00000002 /* 2: HSI14 clock ready */
|
#define RCC_CR2_HSI14RDY 0x00000002 /* 2: HSI14 clock ready */
|
||||||
|
|
||||||
|
|
||||||
|
#define CRC ((volatile unsigned *) 0x40023000)
|
||||||
|
#define CRC_DR CRC[ 0]
|
||||||
|
#define CRC_IDR CRC[ 1]
|
||||||
|
#define CRC_CR CRC[ 2]
|
||||||
|
#define CRC_INIT CRC[ 4]
|
||||||
|
|
||||||
|
|
||||||
#define GPIOA ((volatile long *) 0x48000000)
|
#define GPIOA ((volatile long *) 0x48000000)
|
||||||
#define GPIOB ((volatile long *) 0x48000400)
|
#define GPIOB ((volatile long *) 0x48000400)
|
||||||
#define GPIO( x) CAT( GPIO, x)
|
#define GPIO( x) CAT( GPIO, x)
|
||||||
@ -108,7 +116,8 @@
|
|||||||
|
|
||||||
/** SYSTEM MEMORY *************************************************************/
|
/** SYSTEM MEMORY *************************************************************/
|
||||||
/* STM32F030 calibration addresses (at 3.3V and 30C) */
|
/* STM32F030 calibration addresses (at 3.3V and 30C) */
|
||||||
#define TS_CAL ((unsigned short *) 0x1FFFF7B8)
|
#define TS_CAL ((const unsigned short *) 0x1FFFF7B8)
|
||||||
#define VREFINT_CAL ((unsigned short *) 0x1FFFF7BA)
|
#define VREFINT_CAL ((const unsigned short *) 0x1FFFF7BA)
|
||||||
|
#define TS_CAL2 ((const unsigned short *) 0x1FFFF7C2)
|
||||||
|
|
||||||
/* end of stm32f030xx.h */
|
/* end of stm32f030xx.h */
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user