Support BOOT, GOFLASH and GORAM memory models.
This commit is contained in:
parent
726f4bf316
commit
55a48fd471
43
Makefile
43
Makefile
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@ -39,7 +39,22 @@ SIZE = $(BINPFX)size
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### STM32F030F4P6 based board
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PROJECT = f030f4
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PROJECT = f030f4.$(FLASHSTART)
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# In RAM Execution, Bootloader uses first 2K of RAM
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#FLASHSTART = 0x20000800
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#FLASHSIZE = 2K
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#RAMSTART = 0x20000000
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#RAMSIZE = 2K
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#RAMISRV = 1
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# In Flash Execution, ISR vector copied and mapped to RAM if RAMISRV is not 0
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FLASHSTART = 0x08000000
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FLASHSIZE = 16K
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RAMSTART = 0x20000000
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RAMSIZE = 4K
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#RAMISRV = 1
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#SRCS = boot.c
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#SRCS = ledon.c
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#SRCS = blink.c
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@ -57,12 +72,21 @@ PROJECT = f030f4
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#SRCS = startup.txeie.c gpioa.c dht11main.c dht11.c
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#SRCS = startup.txeie.c gpioa.c ds18b20main.c ds18b20.c
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#SRCS = startup.txeie.c adc.c adcmain.c
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SRCS = startup.txeie.c adc.c adccalib.c ds18b20.c
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#SRCS = startup.txeie.c adc.c adccalib.c ds18b20.c
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SRCS = startup.ram.c txeie.c uptime.1.c
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OBJS = $(SRCS:.c=.o)
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LIBOBJS = printf.o putchar.o puts.o memset.o
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LIBOBJS = printf.o putchar.o puts.o memset.o memcpy.o
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CPU = -mthumb -mcpu=cortex-m0
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CFLAGS = $(CPU) -g -Wall -Wextra -Os
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LD_SCRIPT = $(PROJECT).ld
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ifdef RAMISRV
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CDEFINES = -DRAMISRV=$(RAMISRV)
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endif
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WARNINGS=-pedantic -Wall -Wextra -Wstrict-prototypes -Wno-unused-parameter
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CFLAGS = $(CPU) -g $(WARNINGS) -Os $(CDEFINES)
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LD_SCRIPT = generic.ld
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LDDEFS = --defsym,FLASHSTART=$(FLASHSTART),--defsym,FLASHSIZE=$(FLASHSIZE)
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LDDEFINES = $(LDDEFS),--defsym,RAMSTART=$(RAMSTART),--defsym,RAMSIZE=$(RAMSIZE)
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LIBSTEM = stm32
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LIBS = -l$(LIBSTEM)
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@ -75,6 +99,7 @@ all: $(PROJECT).hex $(PROJECT).bin
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version:
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@echo make $(MAKE_VERSION) $(MAKE_HOST)
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@echo PATH="$(PATH)"
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$(CC) --version
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clean:
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@echo CLEAN
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@ -82,15 +107,15 @@ clean:
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$(PROJECT).elf: $(OBJS) lib$(LIBSTEM).a
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@echo $@
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$(CC) $(CPU) -T$(LD_SCRIPT) -L. -Wl,-Map=$(PROJECT).map,-cref \
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-nostartfiles -o $@ $(OBJS) $(LIBS)
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$(CC) $(CPU) -T$(LD_SCRIPT) -L. -Wl,$(LDDEFINES),-Map=$(PROJECT).map,-cref \
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-nostartfiles -o $@ $(OBJS) $(LIBS)
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$(SIZE) $@
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$(OBJDUMP) -hS $@ > $(PROJECT).lst
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%.elf: %.o lib$(LIBSTEM).a
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@echo $@
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$(CC) $(CPU) -T$(LD_SCRIPT) -L. -Wl,-Map=$*.map,-cref -nostartfiles \
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-o $@ $< $(LIBS)
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$(CC) $(CPU) -T$(LD_SCRIPT) -L. -Wl,$(LDDEFINES),-Map=$*.map,-cref \
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-nostartfiles -o $@ $< $(LIBS)
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$(SIZE) $@
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$(OBJDUMP) -hS $@ > $*.lst
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@ -0,0 +1,209 @@
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/* f030f4.ram.ld -- STM32F030F4 in RAM execution linker script */
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/* Copyright (c) 2021 Renaud Fivet */
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/* Linker script to configure memory regions.
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* Need modifying for a specific board.
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* FLASH.ORIGIN: starting address of flash
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* FLASH.LENGTH: length of flash
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* RAM.ORIGIN: starting address of RAM bank 0
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* RAM.LENGTH: length of RAM bank 0
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*/
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x20000800, LENGTH = 2K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 2K
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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KEEP(*(.isr_vector))
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*(.text*)
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*(.init)
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*(.fini)
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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*(.eh_frame*)
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. = ALIGN(4);
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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/* To copy multiple ROM to RAM sections,
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* uncomment .copy.table section and,
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* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
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/*
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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LONG (__etext2)
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LONG (__data2_start__)
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LONG (__data2_end__ - __data2_start__)
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__copy_table_end__ = .;
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} > FLASH
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*/
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/* To clear multiple BSS sections,
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* uncomment .zero.table section and,
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* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
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/*
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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LONG (__bss2_start__)
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LONG (__bss2_end__ - __bss2_start__)
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__zero_table_end__ = .;
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} > FLASH
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*/
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/* Location counter can end up 2byte aligned with narrow Thumb code but
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__etext is assumed by startup code to be the LMA of a section in RAM
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which must be 4byte aligned */
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__etext = ALIGN (4);
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/* In RAM isr vector reserved space at beginning of RAM */
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.isrdata :
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{
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ram_vector = . ;
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. = . + 192 ;
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} > RAM
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.data : AT (__etext)
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{
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__data_start__ = .;
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*(vtable)
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*(.data*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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*(.preinit_array)
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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*(SORT(.init_array.*))
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*(.init_array)
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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*(SORT(.fini_array.*))
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*(.fini_array)
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PROVIDE_HIDDEN (__fini_array_end = .);
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*(.jcr)
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM
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.bss :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > RAM
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.heap (COPY):
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{
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__end__ = .;
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PROVIDE(end = .);
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*(.heap*)
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__HeapLimit = .;
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} > RAM
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (COPY):
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{
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*(.stack*)
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} > RAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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PROVIDE(__data_size = __bss_start__ - __data_start__);
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PROVIDE(__bss_size = __bss_end__ - __bss_start__);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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/* end of f030f4.ram.ld */
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@ -0,0 +1,209 @@
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/* generic.ld -- parametrized linker script */
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/* Copyright (c) 2021 Renaud Fivet */
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/* Linker script to configure memory regions.
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* Need modifying for a specific board.
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* FLASH.ORIGIN: starting address of flash
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* FLASH.LENGTH: length of flash
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* RAM.ORIGIN: starting address of RAM bank 0
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* RAM.LENGTH: length of RAM bank 0
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*/
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MEMORY
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{
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/* FLASH means code, read only data and data initialization */
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FLASH (rx) : ORIGIN = FLASHSTART, LENGTH = FLASHSIZE
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RAM (rwx) : ORIGIN = RAMSTART, LENGTH = RAMSIZE
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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KEEP(*(.isr_vector))
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*(.text*)
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*(.init)
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*(.fini)
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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*(.eh_frame*)
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. = ALIGN(4);
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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/* To copy multiple ROM to RAM sections,
|
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* uncomment .copy.table section and,
|
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* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
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/*
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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LONG (__etext2)
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LONG (__data2_start__)
|
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LONG (__data2_end__ - __data2_start__)
|
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__copy_table_end__ = .;
|
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} > FLASH
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*/
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|
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/* To clear multiple BSS sections,
|
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* uncomment .zero.table section and,
|
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* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
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/*
|
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.zero.table :
|
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{
|
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. = ALIGN(4);
|
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__zero_table_start__ = .;
|
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LONG (__bss_start__)
|
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LONG (__bss_end__ - __bss_start__)
|
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LONG (__bss2_start__)
|
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LONG (__bss2_end__ - __bss2_start__)
|
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__zero_table_end__ = .;
|
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} > FLASH
|
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*/
|
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|
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/* Location counter can end up 2byte aligned with narrow Thumb code but
|
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__etext is assumed by startup code to be the LMA of a section in RAM
|
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which must be 4byte aligned */
|
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__etext = ALIGN (4);
|
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|
||||
/* In RAM isr vector reserved space at beginning of RAM */
|
||||
.isrdata (COPY):
|
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{
|
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KEEP(*(.ram_vector))
|
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} > RAM
|
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|
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.data : AT (__etext)
|
||||
{
|
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__data_start__ = .;
|
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*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
*(.preinit_array)
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
*(SORT(.init_array.*))
|
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*(.init_array)
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
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|
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. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
*(SORT(.fini_array.*))
|
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*(.fini_array)
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
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|
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*(.jcr)
|
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. = ALIGN(4);
|
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/* All data end */
|
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__data_end__ = .;
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|
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} > RAM
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|
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.bss :
|
||||
{
|
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. = ALIGN(4);
|
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__bss_start__ = .;
|
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*(.bss*)
|
||||
*(COMMON)
|
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. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
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|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
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PROVIDE(__stack = __StackTop);
|
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PROVIDE(__data_size = __bss_start__ - __data_start__);
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PROVIDE(__bss_size = __bss_end__ - __bss_start__);
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|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
||||
/* end of generic.ld */
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/* memcpy.c -- copy memory area */
|
||||
/* Copyright (c) 2021 Renaud Fivet */
|
||||
|
||||
#include <string.h>
|
||||
|
||||
void *memcpy( void *to, const void *from, size_t n) {
|
||||
const char *s = from ;
|
||||
char *d = to ;
|
||||
while( n--)
|
||||
*d++ = *s++ ;
|
||||
|
||||
return to ;
|
||||
}
|
||||
|
||||
/* end of memcpy.c */
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/* startup.ram.c -- entry point at reset and C startup
|
||||
** Copyright (c) 2020-2021 Renaud Fivet
|
||||
** v7: isr vector mapped to RAM to enable in RAM execution
|
||||
** v6: device specific interrupts mapped
|
||||
** v5: System Exceptions mapped
|
||||
** v4: calls to init() and main()
|
||||
** v3: data and bss RAM memory initialization
|
||||
** v2: SysTick System Exception mapped
|
||||
** v1: stack and entry point
|
||||
*/
|
||||
|
||||
#include "system.h" /* init() */
|
||||
#include "stm32f030xx.h"
|
||||
|
||||
/* Memory locations defined by linker script */
|
||||
void __StackTop( void) ; /* __StackTop points after end of stack */
|
||||
void Reset_Handler( void) ; /* Entry point for execution */
|
||||
extern const long __etext[] ; /* start of initialized data copy in flash */
|
||||
extern long __data_start__[] ;
|
||||
extern long __bss_start__[] ;
|
||||
extern long __bss_end__ ; /* &__bss_end__ points after end of bss */
|
||||
|
||||
/* Stubs for System Exception Handler */
|
||||
void Default_Handler( void) ;
|
||||
#define dflt_hndlr( fun) void fun##_Handler( void) \
|
||||
__attribute__((weak,alias("Default_Handler")))
|
||||
dflt_hndlr( NMI) ;
|
||||
dflt_hndlr( HardFault) ;
|
||||
dflt_hndlr( SVCall) ;
|
||||
dflt_hndlr( PendSV) ;
|
||||
dflt_hndlr( SysTick) ;
|
||||
|
||||
dflt_hndlr( WWDG) ;
|
||||
dflt_hndlr( RTC) ;
|
||||
dflt_hndlr( FLASH) ;
|
||||
dflt_hndlr( RCC) ;
|
||||
dflt_hndlr( EXTI0_1) ;
|
||||
dflt_hndlr( EXTI2_3) ;
|
||||
dflt_hndlr( EXTI4_15) ;
|
||||
dflt_hndlr( DMA_CH1) ;
|
||||
dflt_hndlr( DMA_CH2_3) ;
|
||||
dflt_hndlr( DMA_CH4_5) ;
|
||||
dflt_hndlr( ADC) ;
|
||||
dflt_hndlr( TIM1_BRK_UP_TRG_COM) ;
|
||||
dflt_hndlr( TIM1_CC) ;
|
||||
dflt_hndlr( TIM3) ;
|
||||
dflt_hndlr( TIM6) ;
|
||||
dflt_hndlr( TIM14) ;
|
||||
dflt_hndlr( TIM15) ;
|
||||
dflt_hndlr( TIM16) ;
|
||||
dflt_hndlr( TIM17) ;
|
||||
dflt_hndlr( I2C1) ;
|
||||
dflt_hndlr( I2C2) ;
|
||||
dflt_hndlr( SPI1) ;
|
||||
dflt_hndlr( SPI2) ;
|
||||
dflt_hndlr( USART1) ;
|
||||
dflt_hndlr( USART2) ;
|
||||
dflt_hndlr( USART3_4_5_6) ;
|
||||
dflt_hndlr( USB) ;
|
||||
|
||||
/* Interrupt vector table:
|
||||
* 1 Stack Pointer reset value
|
||||
* 15 System Exceptions
|
||||
* 32 Device specific Interrupts
|
||||
*/
|
||||
typedef void (*isr_p)( void) ;
|
||||
isr_p const isr_vector[ 16 + 32] __attribute__((section(".isr_vector"))) = {
|
||||
__StackTop,
|
||||
/* System Exceptions */
|
||||
Reset_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
0, 0, 0, 0, 0, 0, 0,
|
||||
SVCall_Handler,
|
||||
0, 0,
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
/* STM32F030xx specific Interrupts cf RM0360 */
|
||||
WWDG_Handler,
|
||||
0,
|
||||
RTC_Handler,
|
||||
FLASH_Handler,
|
||||
RCC_Handler,
|
||||
EXTI0_1_Handler,
|
||||
EXTI2_3_Handler,
|
||||
EXTI4_15_Handler,
|
||||
0,
|
||||
DMA_CH1_Handler,
|
||||
DMA_CH2_3_Handler,
|
||||
DMA_CH4_5_Handler,
|
||||
ADC_Handler,
|
||||
TIM1_BRK_UP_TRG_COM_Handler,
|
||||
TIM1_CC_Handler,
|
||||
0,
|
||||
TIM3_Handler,
|
||||
TIM6_Handler,
|
||||
0,
|
||||
TIM14_Handler,
|
||||
TIM15_Handler,
|
||||
TIM16_Handler,
|
||||
TIM17_Handler,
|
||||
I2C1_Handler,
|
||||
I2C2_Handler,
|
||||
SPI1_Handler,
|
||||
SPI2_Handler,
|
||||
USART1_Handler,
|
||||
USART2_Handler,
|
||||
USART3_4_5_6_Handler,
|
||||
0,
|
||||
USB_Handler
|
||||
} ;
|
||||
|
||||
#if RAMISRV
|
||||
# define ISRV_SIZE (sizeof isr_vector / sizeof *isr_vector)
|
||||
isr_p ram_vector[ ISRV_SIZE] __attribute__((section(".ram_vector"))) ;
|
||||
#endif
|
||||
|
||||
int main( void) ;
|
||||
|
||||
void Reset_Handler( void) {
|
||||
const long *f ; /* from, source constant data from FLASH */
|
||||
long *t ; /* to, destination in RAM */
|
||||
|
||||
#if RAMISRV
|
||||
/* Copy isr vector to beginning of RAM */
|
||||
for( unsigned i = 0 ; i < ISRV_SIZE ; i++)
|
||||
ram_vector[ i] = isr_vector[ i] ;
|
||||
#endif
|
||||
|
||||
/* Assume:
|
||||
** __bss_start__ == __data_end__
|
||||
** All sections are 4 bytes aligned
|
||||
*/
|
||||
f = __etext ;
|
||||
for( t = __data_start__ ; t < __bss_start__ ; t += 1)
|
||||
*t = *f++ ;
|
||||
|
||||
while( t < &__bss_end__)
|
||||
*t++ = 0 ;
|
||||
|
||||
/* Make sure active isr vector is mapped at 0x0 before enabling interrupts */
|
||||
RCC_APB2ENR |= RCC_APB2ENR_SYSCFGEN ; /* Enable SYSCFG */
|
||||
#if RAMISRV
|
||||
SYSCFG_CFGR1 |= 3 ; /* Map RAM at 0x0 */
|
||||
#else
|
||||
SYSCFG_CFGR1 &= ~3 ; /* Map FLASH at 0x0 */
|
||||
#endif
|
||||
|
||||
if( init() == 0)
|
||||
main() ;
|
||||
|
||||
for( ;;)
|
||||
__asm( "WFI") ; /* Wait for interrupt */
|
||||
}
|
||||
|
||||
void Default_Handler( void) {
|
||||
for( ;;) ;
|
||||
}
|
||||
|
||||
/* end of startup.ram.c */
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/* stm32f030xx.h -- STM32F030xx specific mapping */
|
||||
/* Copyright (c) 2021 Renaud Fivet */
|
||||
|
||||
/** CORE **********************************************************************/
|
||||
|
||||
#define SYSTICK ((volatile unsigned long *) 0xE000E010)
|
||||
#define SYSTICK_CSR SYSTICK[ 0]
|
||||
#define SYSTICK_RVR SYSTICK[ 1]
|
||||
#define SYSTICK_CVR SYSTICK[ 2]
|
||||
|
||||
#define NVIC ((volatile long *) 0xE000E100)
|
||||
#define NVIC_ISER NVIC[ 0]
|
||||
#define unmask_irq( idx) NVIC_ISER = 1 << idx
|
||||
#define USART1_IRQ_IDX 27
|
||||
|
||||
|
||||
/** PERIPH ********************************************************************/
|
||||
|
||||
#define CAT( a, b) a##b
|
||||
#define RCC ((volatile long *) 0x40021000)
|
||||
|
||||
#define RCC_CR RCC[ 0]
|
||||
#define RCC_CR_HSION 0x00000001 /* 1: Internal High Speed clock enable */
|
||||
#define RCC_CR_HSEON 0x00010000 /* 16: External High Speed clock enable */
|
||||
#define RCC_CR_HSERDY 0x00020000 /* 17: External High Speed clock ready flag */
|
||||
#define RCC_CR_PLLON 0x01000000 /* 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY 0x02000000 /* 25: PLL clock ready flag */
|
||||
|
||||
#define RCC_CFGR RCC[ 1]
|
||||
#define RCC_CFGR_SW_MSK 0x00000003 /* 1-0: System clock SWitch Mask */
|
||||
#define RCC_CFGR_SW_HSE 0x00000001 /* 1-0: Switch to HSE as system clock */
|
||||
#define RCC_CFGR_SW_PLL 0x00000002 /* 1-0: Switch to PLL as system clock */
|
||||
#define RCC_CFGR_SWS_MSK 0x0000000C /* 3-2: System clock SWitch Status Mask */
|
||||
#define RCC_CFGR_SWS_HSE 0x00000004 /* 3-2: HSE used as system clock */
|
||||
#define RCC_CFGR_SWS_PLL 0x00000008 /* 3-2: PLL used as system clock */
|
||||
#define RCC_CFGR_PLLSRC 0x00010000
|
||||
#define RCC_CFGR_PLLSRC_HSI 0x00000000 /* HSI / 2 */
|
||||
#define RCC_CFGR_PLLSRC_HSE 0x00010000 /* HSE */
|
||||
#define RCC_CFGR_PLLXTPRE 0x00020000
|
||||
#define RCC_CFGR_PLLXTPRE_DIV1 0x00000000 /* HSE */
|
||||
#define RCC_CFGR_PLLXTPRE_DIV2 0x00020000 /* HSE / 2 */
|
||||
#define RCC_CFGR_PLLMUL_MSK (0x00F << 18)
|
||||
#define RCC_CFGR_PLLMUL( v) ((v - 2) << 18)
|
||||
|
||||
#define RCC_AHBENR RCC[ 5]
|
||||
#define RCC_AHBENR_IOPn( n) (1 << (17 + n))
|
||||
#define RCC_AHBENR_IOPh( h) RCC_AHBENR_IOPn( CAT( 0x, h) - 0xA)
|
||||
|
||||
#define RCC_APB2ENR RCC[ 6]
|
||||
#define RCC_APB2ENR_USART1EN 0x00004000 /* 14: USART1 clock enable */
|
||||
#define RCC_APB2ENR_ADCEN 0x00000200 /* 9: ADC clock enable */
|
||||
#define RCC_APB2ENR_SYSCFGEN 0x00000001 /* 1: SYSCFG clock enable */
|
||||
|
||||
#define RCC_CR2 RCC[ 13]
|
||||
#define RCC_CR2_HSI14ON 0x00000001 /* 1: HSI14 clock enable */
|
||||
#define RCC_CR2_HSI14RDY 0x00000002 /* 2: HSI14 clock ready */
|
||||
|
||||
|
||||
#define GPIOA ((volatile long *) 0x48000000)
|
||||
#define GPIOB ((volatile long *) 0x48000400)
|
||||
#define GPIO( x) CAT( GPIO, x)
|
||||
#define MODER 0
|
||||
#define IDR 4
|
||||
#define ODR 5
|
||||
#define AFRH 9
|
||||
|
||||
#define SYSCFG ((volatile long *) 0x40010000)
|
||||
#define SYSCFG_CFGR1 SYSCFG[ 0]
|
||||
|
||||
#define ADC ((volatile long *) 0x40012400)
|
||||
#define ADC_ISR ADC[ 0]
|
||||
#define ADC_ISR_ADRDY 1 /* 0: ADC Ready */
|
||||
#define ADC_ISR_EOC 4 /* 2: End Of Conversion flag */
|
||||
|
||||
#define ADC_CR ADC[ 2]
|
||||
#define ADC_CR_ADEN 1 /* 0: ADc ENable command */
|
||||
#define ADC_CR_ADSTART 4 /* 2: ADC Start Conversion command */
|
||||
#define ADC_CR_ADCAL (1 << 31) /* 31: ADC Start Calibration cmd */
|
||||
|
||||
#define ADC_CFGR1 ADC[ 3] /* Configuration Register 1 */
|
||||
#define ADC_CFGR1_SCANDIR 4 /* 2: Scan sequence direction */
|
||||
#define ADC_CFGR1_DISCEN (1 << 16) /* 16: Enable Discontinuous mode */
|
||||
|
||||
#define ADC_CFGR2 ADC[ 4] /* Configuration Register 2 */
|
||||
#define ADC_CFGR2_CKMODE (3 << 30) /* 31-30: Clock Mode Mask */
|
||||
/* 31-30: Default 00 HSI14 */
|
||||
#define ADC_CFGR2_PCLK2 (1 << 30) /* 31-30: PCLK/2 */
|
||||
#define ADC_CFGR2_PCLK4 (2 << 30) /* 31-30: PCLK/4 */
|
||||
|
||||
#define ADC_SMPR ADC[ 5] /* Sampling Time Register */
|
||||
#define ADC_CHSELR ADC[ 10] /* Channel Selection Register */
|
||||
#define ADC_DR ADC[ 16] /* Data Register */
|
||||
#define ADC_CCR ADC[ 194] /* Common Configuration Register */
|
||||
#define ADC_CCR_VREFEN (1 << 22) /* 22: Vrefint Enable */
|
||||
#define ADC_CCR_TSEN (1 << 23) /* 23: Temperature Sensor Enable */
|
||||
|
||||
#define USART1 ((volatile long *) 0x40013800)
|
||||
#define CR1 0 /* Config Register */
|
||||
#define BRR 3 /* BaudRate Register */
|
||||
#define ISR 7 /* Interrupt and Status Register */
|
||||
#define TDR 10 /* Transmit Data Register*/
|
||||
#define USART_CR1_TXEIE (1 << 7) /* 7: TDR Empty Interrupt Enable */
|
||||
#define USART_CR1_TE 8 /* 3: Transmit Enable */
|
||||
#define USART_CR1_RE 4 /* 2: Receive Enable */
|
||||
#define USART_CR1_UE 1 /* 0: USART Enable */
|
||||
#define USART_ISR_TXE (1 << 7) /* 7: Transmit Data Register Empty */
|
||||
|
||||
|
||||
/** SYSTEM MEMORY *************************************************************/
|
||||
/* STM32F030 calibration addresses (at 3.3V and 30C) */
|
||||
#define TS_CAL ((unsigned short *) 0x1FFFF7B8)
|
||||
#define VREFINT_CAL ((unsigned short *) 0x1FFFF7BA)
|
||||
|
||||
/* end of stm32f030xx.h */
|
||||
Loading…
Reference in New Issue