a5dcdfacc2
MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you can use Python as a hardware description and verification language. Furthermore, you can convert MyHDL code, that was developed towards implementation, to Verilog and VHDL automatically, and take it to a silicon implementation from there. ok landry@
31 lines
751 B
Makefile
31 lines
751 B
Makefile
# $OpenBSD: Makefile,v 1.1.1.1 2011/09/16 13:46:13 jasper Exp $
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COMMENT= Python as a hardware description and verification language
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MODPY_EGG_VERSION=0.7
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DISTNAME= myhdl-${MODPY_EGG_VERSION}
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CATEGORIES= lang
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HOMEPAGE= http://www.myhdl.org/
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# LGPLv2.1
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PERMIT_PACKAGE_FTP= Yes
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PERMIT_PACKAGE_CDROM= Yes
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PERMIT_DISTFILES_FTP= Yes
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PERMIT_DISTFILES_CDROM= Yes
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MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/}
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MODULES+= lang/python
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post-install:
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${INSTALL_DATA_DIR} ${PREFIX}/share/examples/myhdl/
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cd ${WRKSRC}/example/ && umask 022 && pax -rw . \
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${PREFIX}/share/examples/myhdl/
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do-regress: fake
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cd ${WRKSRC}/myhdl/test/core && \
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env PYTHONPATH="${WRKINST}${MODPY_LIBDIR}/site-packages/" \
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${MODPY_BIN} test_all.py
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.include <bsd.port.mk>
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