import myhdl 0.7

MyHDL is an open source Python package that lets you go from Python to
silicon. With MyHDL, you can use Python as a hardware description and
verification language. Furthermore, you can convert MyHDL code, that was
developed towards implementation, to Verilog and VHDL automatically, and
take it to a silicon implementation from there.

ok landry@
This commit is contained in:
jasper 2011-09-16 13:46:13 +00:00
parent d234fdd40e
commit a5dcdfacc2
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# $OpenBSD: Makefile,v 1.1.1.1 2011/09/16 13:46:13 jasper Exp $
COMMENT= Python as a hardware description and verification language
MODPY_EGG_VERSION=0.7
DISTNAME= myhdl-${MODPY_EGG_VERSION}
CATEGORIES= lang
HOMEPAGE= http://www.myhdl.org/
# LGPLv2.1
PERMIT_PACKAGE_FTP= Yes
PERMIT_PACKAGE_CDROM= Yes
PERMIT_DISTFILES_FTP= Yes
PERMIT_DISTFILES_CDROM= Yes
MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/}
MODULES+= lang/python
post-install:
${INSTALL_DATA_DIR} ${PREFIX}/share/examples/myhdl/
cd ${WRKSRC}/example/ && umask 022 && pax -rw . \
${PREFIX}/share/examples/myhdl/
do-regress: fake
cd ${WRKSRC}/myhdl/test/core && \
env PYTHONPATH="${WRKINST}${MODPY_LIBDIR}/site-packages/" \
${MODPY_BIN} test_all.py
.include <bsd.port.mk>

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MD5 (myhdl-0.7.tar.gz) = Da1pD+Fl5OjUtCFVtoL7Yw==
RMD160 (myhdl-0.7.tar.gz) = xSWyGobJIE7Hz2WXCbwOj7LHRQs=
SHA1 (myhdl-0.7.tar.gz) = Q4JEQjApdZPwoIuoF4xUK0zh8Zs=
SHA256 (myhdl-0.7.tar.gz) = fT4ONjpX5c6G9z9RUhXDA45n4AgqzhIM4Ah4+ljyc2g=
SIZE (myhdl-0.7.tar.gz) = 241770

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MyHDL is an open source Python package that lets you go from Python to
silicon. With MyHDL, you can use Python as a hardware description and
verification language. Furthermore, you can convert MyHDL code, that was
developed towards implementation, to Verilog and VHDL automatically, and
take it to a silicon implementation from there.

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@comment $OpenBSD: PLIST,v 1.1.1.1 2011/09/16 13:46:13 jasper Exp $
lib/python${MODPY_VERSION}/site-packages/myhdl/
lib/python${MODPY_VERSION}/site-packages/myhdl-${MODPY_EGG_VERSION}-py${MODPY_VERSION}.egg-info
lib/python${MODPY_VERSION}/site-packages/myhdl/_Cosimulation.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_Cosimulation.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_ShadowSignal.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_ShadowSignal.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_Signal.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_Signal.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_Simulation.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_Simulation.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_Waiter.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_Waiter.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/__init__.py
lib/python${MODPY_VERSION}/site-packages/myhdl/__init__.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_always.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_always.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_always_comb.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_always_comb.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_bin.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_bin.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_cell_deref.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_cell_deref.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_concat.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_concat.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_delay.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_delay.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_enum.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_enum.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_extractHierarchy.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_extractHierarchy.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_instance.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_instance.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_intbv.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_intbv.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_join.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_join.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_misc.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_misc.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_simulator.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_simulator.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_traceSignals.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_traceSignals.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_tristate.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_tristate.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_unparse.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_unparse.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/_util.py
lib/python${MODPY_VERSION}/site-packages/myhdl/_util.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/__init__.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/__init__.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_analyze.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_analyze.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_misc.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_misc.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_toVHDL.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_toVHDL.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_toVHDLPackage.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_toVHDLPackage.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_toVerilog.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_toVerilog.pyc
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_verify.py
lib/python${MODPY_VERSION}/site-packages/myhdl/conversion/_verify.pyc
share/examples/myhdl/
share/examples/myhdl/arith_lib/
share/examples/myhdl/arith_lib/Dec.py
share/examples/myhdl/arith_lib/LeadZeroDet.py
share/examples/myhdl/arith_lib/PrefixAnd.py
share/examples/myhdl/arith_lib/README.txt
share/examples/myhdl/arith_lib/__init__.py
share/examples/myhdl/arith_lib/arith_utils.py
share/examples/myhdl/arith_lib/test_Dec.py
share/examples/myhdl/arith_lib/test_LeadZeroDet.py
share/examples/myhdl/cookbook/
share/examples/myhdl/cookbook/README.txt
share/examples/myhdl/cookbook/bitonic/
share/examples/myhdl/cookbook/bitonic/Array8Sorter.v
share/examples/myhdl/cookbook/bitonic/Array8Sorter.vhd
share/examples/myhdl/cookbook/bitonic/bitonic.py
share/examples/myhdl/cookbook/bitonic/pck_myhdl_07dev.vhd
share/examples/myhdl/cookbook/bitonic/tb_Array8Sorter.v
share/examples/myhdl/cookbook/bitonic/test_bitonic.py
share/examples/myhdl/cookbook/dff/
share/examples/myhdl/cookbook/dff/dff.py
share/examples/myhdl/cookbook/dff/dff.v
share/examples/myhdl/cookbook/dff/dff.vhd
share/examples/myhdl/cookbook/dff/pck_myhdl_07dev.vhd
share/examples/myhdl/cookbook/dff/tb_dff.v
share/examples/myhdl/cookbook/dffa/
share/examples/myhdl/cookbook/dffa/dffa.py
share/examples/myhdl/cookbook/johnson/
share/examples/myhdl/cookbook/johnson/jc2.py
share/examples/myhdl/cookbook/johnson/jc2.v
share/examples/myhdl/cookbook/johnson/jc2.vhd
share/examples/myhdl/cookbook/johnson/jc2_alt.py
share/examples/myhdl/cookbook/johnson/jc2_alt.v
share/examples/myhdl/cookbook/johnson/jc2_alt.vhd
share/examples/myhdl/cookbook/johnson/pck_myhdl_07dev.vhd
share/examples/myhdl/cookbook/johnson/tb_jc2.v
share/examples/myhdl/cookbook/johnson/tb_jc2_alt.v
share/examples/myhdl/cookbook/johnson/test_jc2.py
share/examples/myhdl/cookbook/latch/
share/examples/myhdl/cookbook/latch/latch.py
share/examples/myhdl/cookbook/latch/latch.v
share/examples/myhdl/cookbook/latch/latch.vhd
share/examples/myhdl/cookbook/latch/pck_myhdl_07dev.vhd
share/examples/myhdl/cookbook/latch/tb_latch.v
share/examples/myhdl/cookbook/sinecomp/
share/examples/myhdl/cookbook/sinecomp/SineComputer.py
share/examples/myhdl/cookbook/sinecomp/SineComputer.v
share/examples/myhdl/cookbook/sinecomp/SineComputer.vhd
share/examples/myhdl/cookbook/sinecomp/pck_myhdl_07dev.vhd
share/examples/myhdl/cookbook/sinecomp/tb_SineComputer.v
share/examples/myhdl/cookbook/sinecomp/test_SineComputer.py
share/examples/myhdl/cookbook/stopwatch/
share/examples/myhdl/cookbook/stopwatch/StopWatch.py
share/examples/myhdl/cookbook/stopwatch/TimeCount.py
share/examples/myhdl/cookbook/stopwatch/TimeCount.v
share/examples/myhdl/cookbook/stopwatch/TimeCount.vhd
share/examples/myhdl/cookbook/stopwatch/bcd2led.py
share/examples/myhdl/cookbook/stopwatch/pck_myhdl_07dev.vhd
share/examples/myhdl/cookbook/stopwatch/seven_segment.py
share/examples/myhdl/cookbook/stopwatch/tb_TimeCount.v
share/examples/myhdl/cookbook/stopwatch/test_TimeCount.py
share/examples/myhdl/cookbook/stopwatch/test_bcd2led.py
share/examples/myhdl/manual/
share/examples/myhdl/manual/FramerCtrl.v
share/examples/myhdl/manual/FramerCtrl.vhd
share/examples/myhdl/manual/GrayInc.py
share/examples/myhdl/manual/GrayIncReg.v
share/examples/myhdl/manual/GrayIncReg.vhd
share/examples/myhdl/manual/Inc.v
share/examples/myhdl/manual/Inc.vhd
share/examples/myhdl/manual/Makefile
share/examples/myhdl/manual/bin2gray.py
share/examples/myhdl/manual/bin2gray.v
share/examples/myhdl/manual/bin2gray.vhd
share/examples/myhdl/manual/bin2gray2.py
share/examples/myhdl/manual/custom.py
share/examples/myhdl/manual/fifo.py
share/examples/myhdl/manual/fsm.py
share/examples/myhdl/manual/fsm2.py
share/examples/myhdl/manual/fsm3.py
share/examples/myhdl/manual/greetings.py
share/examples/myhdl/manual/hec.py
share/examples/myhdl/manual/hello1.py
share/examples/myhdl/manual/hello2.py
share/examples/myhdl/manual/inc.py
share/examples/myhdl/manual/inc_comb.v
share/examples/myhdl/manual/inc_comb.vhd
share/examples/myhdl/manual/mux.py
share/examples/myhdl/manual/mux2.py
share/examples/myhdl/manual/pck_myhdl_07.vhd
share/examples/myhdl/manual/queue.py
share/examples/myhdl/manual/ram.py
share/examples/myhdl/manual/ram.vhd
share/examples/myhdl/manual/ram_1.v
share/examples/myhdl/manual/rom.py
share/examples/myhdl/manual/rom.v
share/examples/myhdl/manual/rom.vhd
share/examples/myhdl/manual/rs232.py
share/examples/myhdl/manual/run_all.py
share/examples/myhdl/manual/shadow.py
share/examples/myhdl/manual/sparseMemory.py
share/examples/myhdl/manual/tb_FramerCtrl.v
share/examples/myhdl/manual/tb_GrayIncReg.v
share/examples/myhdl/manual/tb_Inc.v
share/examples/myhdl/manual/tb_bin2gray.v
share/examples/myhdl/manual/tb_inc_comb.v
share/examples/myhdl/manual/tb_ram_1.v
share/examples/myhdl/manual/tb_rom.v
share/examples/myhdl/manual/test_gray.py
share/examples/myhdl/rs232/
share/examples/myhdl/rs232/README.txt
share/examples/myhdl/rs232/rs232_rx.py
share/examples/myhdl/rs232/rs232_tx.py
share/examples/myhdl/rs232/rs232_util.py
share/examples/myhdl/rs232/test_rs232.py