MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you can use Python as a hardware description and verification language. Furthermore, you can convert MyHDL code, that was developed towards implementation, to Verilog and VHDL automatically, and take it to a silicon implementation from there. ok landry@
Documentation for the ports tree: ports(7), packages(7), mirroring-ports(7), library-specs(7), bsd.port.mk(5), port-modules(5). See also the OpenBSD Porter's Handbook http://www.openbsd.org/faq/ports/ $OpenBSD: README,v 1.19 2010/08/31 03:28:43 lum Exp $
Description
Public git conversion mirror of OpenBSD's official cvs ports repository. Pull requests not accepted - send diffs to the ports@ mailing list.
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