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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
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723 B
Plaintext
13 lines
723 B
Plaintext
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
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as a compiler, compiling source code writen in Verilog (IEEE-1364) into
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some target format. For batch simulation, the compiler can generate C++
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code that is compiled and linked with a run time library (called "vvm")
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then executed as a command to run the simulation. For synthesis, the
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compiler generates netlists in the desired format.
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The compiler proper is intended to parse and elaborate design
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descriptions written to the IEEE standard IEEE Std 1364-2000. The
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standard proper is due to be release towards the middle of the year
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2000. This is a fairly large and complex standard, so it will take some
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time for it to get there, but that's the goal.
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