jasper 391401eb77 import verilator-3.824 ... Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. ok aja@		2011-11-13 12:44:04 +00:00
..
pkg	import verilator-3.824	2011-11-13 12:44:04 +00:00
distinfo	import verilator-3.824	2011-11-13 12:44:04 +00:00
Makefile	import verilator-3.824	2011-11-13 12:44:04 +00:00