695182bcdf
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
6 lines
289 B
Plaintext
6 lines
289 B
Plaintext
MD5 (verilog-0.9.2.tar.gz) = 47NAnwp6o4LAv7sBllX2Rw==
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RMD160 (verilog-0.9.2.tar.gz) = 2+wH3Cnfv2nbwEufO7VGdFKStjA=
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SHA1 (verilog-0.9.2.tar.gz) = zmIrV96AJX+3C3/alSmQQ87UUdQ=
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SHA256 (verilog-0.9.2.tar.gz) = MhtvMrVgjXzddFqf+OIfPi7B/rqfDj+S2L1wQtgGR8M=
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SIZE (verilog-0.9.2.tar.gz) = 1127067
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