jasper 695182bcdf import iverilog 0.9.2 ... Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.		2010-07-08 18:58:23 +00:00
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pkg	import iverilog 0.9.2	2010-07-08 18:58:23 +00:00
distinfo	import iverilog 0.9.2	2010-07-08 18:58:23 +00:00
Makefile	import iverilog 0.9.2	2010-07-08 18:58:23 +00:00