anywhere else. The only thing not supported yet is tracing using ptrace(2).
- clean up Makefile and restructure a bit
- VMEM_WARNING when -java is built
- some minor PLIST tweaks
ok espie@
rspec 1 using rspec and rspec 2 using rspec2. Additionally, add
support for ruby and testrb, calling the appropriate binary for the
ruby implementation.
Start checking sanity of MODRUBY_REGRESS entry, using a fatal error
if it is defined and doesn't contain a recognized word.
Instead of RAKE_REGRESS_TARGET and RSPEC_REGRESS_TARGET, just use
MODRUBY_REGRESS_TARGET for all cases. On ruby 1.9, modifying the
environment to always look in the current directory for libraries
(the ruby 1.8 behavior), since many ports depend on that for regress.
Allow ports to set their own regress environment and current directory
using MODRUBY_REGRESS_ENV and MODRUBY_REGRESS_DIR.
which should allow building on arches without enough memory to
generate the ri files. Also, set PKG_ARCH=* for the ri_docs
subpackage, so that such arches can still use the documentation,
idea from sthen@. Original idea for PSUEDO_FLAVOR from phessler@.
OK sthen@
The spec task requires network access via git, which is not allowed.
Since git isn't needed anymore for regress, remove it from
REGRESS_DEPENDS. The spec task is just commented out in case somone
wants to run it manually.
Set JAVA_HOME and PATH and disable forking so java doesn't crash when
running the test and spec tasks. Don't install the jruby-launcher gem
when running the test and spec tasks, as it fails.
Regress depend on git when running the specs, as it needs to download
current rubyspecs for the spec task.
Delete the jruby-complete.jar file and just use the jruby.jar file
when running the specs, as otherwise you get additional test failures
and warnings.
Switch to SUBST_CMD while here now that has been fixed. Also, bump
the memory limits by 50M as 384M doesn't seem to be enough in all
cases.
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.
ok aja@
upstream decided to move to separate modules instead
of one monolithic jar file. packaging all these standalone modules is not going
to work, so please use devel/leiningen instead to fetch individual modules.
