openbsd-ports

cpet/openbsd-ports

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Author	SHA1	Message	Date
espie	88dd25abf4	USE_GROFF=Yes	2010-10-18 19:20:41 +00:00
jasper	695182bcdf	import iverilog 0.9.2 Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.	2010-07-08 18:58:23 +00:00

Author

SHA1

Message

Date

espie

88dd25abf4

USE_GROFF=Yes

2010-10-18 19:20:41 +00:00

jasper

695182bcdf

import iverilog 0.9.2

Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code writen in Verilog (IEEE-1364) into
some target format. For batch simulation, the compiler can generate C++
code that is compiled and linked with a run time library (called "vvm")
then executed as a command to run the simulation. For synthesis, the
compiler generates netlists in the desired format.

2010-07-08 18:58:23 +00:00

2 Commits