freebsd-ports/cad/Makefile
Yuri Victorovich 1ca077dcab MFH: r522114 r522170 r522177 r522178
New port: cad/cascade-compiler: Just-In-Time Compiler for Verilog from VMware Research

cad/cascade-compiler: Update g20200104 -> g20200105

Tests now pass.

Fix build on GCC-based systems:

  CMake Error in src/CMakeLists.txt:
  Target "libcascade" requires the language dialect "CXX17" (with compiler
  extensions), but CMake does not know the compile flags to use to enable it.

Approved by:	portmgr (tier-2 blanket)

cad/cascade-compiler: Update g20200105 -> g20200105.1

Approved by:	secteam
2020-01-06 01:52:57 +00:00

116 lines
2.6 KiB
Makefile

# $FreeBSD$
#
COMMENT = CAD tools
SUBDIR += NASTRAN-95
SUBDIR += abc
SUBDIR += admesh
SUBDIR += adms
SUBDIR += alliance
SUBDIR += astk-client
SUBDIR += astk-serveur
SUBDIR += atlc
SUBDIR += basicdsp
SUBDIR += brickutils
SUBDIR += brlcad
SUBDIR += calculix
SUBDIR += calculix-ccx
SUBDIR += caneda
SUBDIR += cascade
SUBDIR += cascade-compiler
SUBDIR += chipvault
SUBDIR += cura-engine
SUBDIR += digital
SUBDIR += dinotrace
SUBDIR += electric
SUBDIR += electric-ng
SUBDIR += elmerfem
SUBDIR += fasm
SUBDIR += feappv
SUBDIR += fidocadj
SUBDIR += freecad
SUBDIR += freehdl
SUBDIR += fritzing
SUBDIR += gdsreader
SUBDIR += gdt
SUBDIR += geda
SUBDIR += ghdl
SUBDIR += gmsh
SUBDIR += gnucap
SUBDIR += gplcver
SUBDIR += gspiceui
SUBDIR += gtkwave
SUBDIR += impact
SUBDIR += irsim
SUBDIR += iverilog
SUBDIR += jspice3
SUBDIR += k40-whisperer
SUBDIR += kicad
SUBDIR += kicad-devel
SUBDIR += kicad-doc
SUBDIR += kicad-library-footprints
SUBDIR += kicad-library-footprints-devel
SUBDIR += kicad-library-packages3d
SUBDIR += kicad-library-packages3d-devel
SUBDIR += kicad-library-symbols
SUBDIR += kicad-library-symbols-devel
SUBDIR += kicad-library-templates
SUBDIR += kicad-library-templates-devel
SUBDIR += klayout
SUBDIR += ktechlab
SUBDIR += ldraw
SUBDIR += leocad
SUBDIR += lepton-eda
SUBDIR += libopencad
SUBDIR += librecad
SUBDIR += libredwg
SUBDIR += librepcb
SUBDIR += linux-eagle5
SUBDIR += linuxcnc-devel
SUBDIR += logisim
SUBDIR += magic
SUBDIR += meshdev
SUBDIR += netgen
SUBDIR += ngspice_rework
SUBDIR += nvc
SUBDIR += opencascade
SUBDIR += openscad
SUBDIR += openscad-devel
SUBDIR += openvsp
SUBDIR += oregano
SUBDIR += p5-GDS2
SUBDIR += p5-Verilog-Perl
SUBDIR += pcb
SUBDIR += pdnmesh
SUBDIR += py-gdspy
SUBDIR += py-lcapy
SUBDIR += py-phidl
SUBDIR += py-pycam
SUBDIR += py-pyfda
SUBDIR += python-gdsii
SUBDIR += pythoncad
SUBDIR += qcad
SUBDIR += qelectrotech
SUBDIR += qmls
SUBDIR += repsnapper
SUBDIR += rubygem-gdsii
SUBDIR += scotch
SUBDIR += solvespace
SUBDIR += sp2sp
SUBDIR += spice
SUBDIR += stepcode
SUBDIR += sumo
SUBDIR += sweethome3d
SUBDIR += tkgate
SUBDIR += tochnog
SUBDIR += transcalc
SUBDIR += varkon
SUBDIR += verilator
SUBDIR += verilog-mode.el
SUBDIR += xcircuit
SUBDIR += z88
SUBDIR += zcad
.include <bsd.port.subdir.mk>