MFH: r522114 r522170 r522177 r522178

New port: cad/cascade-compiler: Just-In-Time Compiler for Verilog from VMware Research

cad/cascade-compiler: Update g20200104 -> g20200105

Tests now pass.

Fix build on GCC-based systems:

  CMake Error in src/CMakeLists.txt:
  Target "libcascade" requires the language dialect "CXX17" (with compiler
  extensions), but CMake does not know the compile flags to use to enable it.

Approved by:	portmgr (tier-2 blanket)

cad/cascade-compiler: Update g20200105 -> g20200105.1

Approved by:	secteam

cad/Makefile

@@ -18,6 +18,7 @@
     SUBDIR += calculix-ccx
     SUBDIR += caneda
     SUBDIR += cascade
+    SUBDIR += cascade-compiler
     SUBDIR += chipvault
     SUBDIR += cura-engine
     SUBDIR += digital

cad/cascade-compiler/Makefile

@@ -0,0 +1,42 @@
+# $FreeBSD$
+
+PORTNAME=	cascade
+PORTVERSION=	g20200105.1
+CATEGORIES=	cad
+PKGNAMESUFFIX=	-compiler
+
+MAINTAINER=	yuri@FreeBSD.org
+COMMENT=	Just-In-Time Compiler for Verilog from VMware Research
+
+LICENSE=	BSD2CLAUSE
+LICENSE_FILE=	${WRKSRC}/LICENSE.txt
+
+BUILD_DEPENDS=	flex>0:textproc/flex
+RUN_DEPENDS=	verilator:cad/verilator
+TEST_DEPENDS=	benchmark>0:devel/benchmark \
+		googletest>0:devel/googletest
+
+USES=		bison cmake compiler:c++17-lang localbase:ldflags ncurses perl5
+USE_GITHUB=	yes
+GH_ACCOUNT=	vmware
+GH_TAGNAME=	f4f7ae8bd1dd379790c0e58c286df90b8d1cdcde
+
+MAKE_ENV=	FREEBSD_WRKSRC=${WRKSRC} FREEBSD_LOCALBASE=${LOCALBASE}
+
+CMAKE_OFF=	BUILD_TESTING
+
+BINARY_ALIAS=	flex=${FILESDIR}/flex flex.real=${LOCALBASE}/bin/flex bison=${LOCALBASE}/bin/bison
+
+post-patch:
+	# cascade needs the latest flex, not one from the base system
+	@${FIND} ${WRKSRC} -name "*.h" | ${XARGS} ${REINPLACE_CMD} -i '' 's|#include <FlexLexer.h>|#include <${LOCALBASE}/include/flex/FlexLexer.h>|'
+	# don't need bash: https://github.com/vmware/cascade/issues/207
+	@${FIND} ${WRKSRC} -name "*.sh" | ${XARGS} ${REINPLACE_CMD} -i '' 's|#!/bin/bash|#!/bin/sh|'
+
+do-test:
+	cd ${BUILD_WRKSRC} && \
+		${SETENV} ${CONFIGURE_ENV} ${CMAKE_BIN} ${CMAKE_ARGS} -DBUILD_TESTING:BOOL=ON ${CMAKE_SOURCE_PATH} && \
+		${SETENV} ${MAKE_ENV} ${MAKE_CMD} ${MAKE_ARGS} ${ALL_TARGET} && \
+		${SETENV} ${MAKE_ENV} ${MAKE_CMD} ${MAKE_ARGS} test
+
+.include <bsd.port.mk>

cad/cascade-compiler/distinfo

@@ -0,0 +1,3 @@
+TIMESTAMP = 1578272762
+SHA256 (vmware-cascade-g20200105.1-f4f7ae8bd1dd379790c0e58c286df90b8d1cdcde_GH0.tar.gz) = b76107bebbe2c9f8737a652ff4e3c8ebf3fcbf13f672b34aa65c9899e7ab8442
+SIZE (vmware-cascade-g20200105.1-f4f7ae8bd1dd379790c0e58c286df90b8d1cdcde_GH0.tar.gz) = 12262109

cad/cascade-compiler/files/flex

@@ -0,0 +1,9 @@
+#!/bin/sh
+
+# $FreeBSD$
+
+# call the real flex
+flex.real "$@"
+
+# update the FlexLexer.h include that the above command must have created
+find ${FREEBSD_WRKSRC} -name "*.cc" | xargs sed -i '' 's|#include <FlexLexer.h>|#include <${FREEBSD_LOCALBASE}/include/flex/FlexLexer.h>|'

cad/cascade-compiler/files/patch-CMakeLists.txt

@@ -0,0 +1,20 @@
+--- CMakeLists.txt.orig	2020-01-06 00:29:10 UTC
++++ CMakeLists.txt
+@@ -35,7 +35,8 @@ set(CMAKE_CXX_FLAGS "-g -O0 -fprofile-arcs -ftest-cove
+ set(CMAKE_C_FLAGS "-g -O0 -fprofile-arcs -ftest-coverage")
+ endif()
+ 
+-include_directories(${FLEX_INCLUDE_DIRS})
++#include_directories(${FLEX_INCLUDE_DIRS}) # cmake always finds base flex header:  https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=243068
++include_directories(${CMAKE_INSTALL_PREFIX}/include/flex)
+ include_directories(${CMAKE_BINARY_DIR}/src)
+ include_directories(.)
+ include_directories(src/cascade)
+@@ -43,5 +44,7 @@ include_directories(src/cascade)
+ add_subdirectory(include)
+ add_subdirectory(share)
+ add_subdirectory(src)
++if(${BUILD_TESTING})
+ add_subdirectory(test)
++endif()
+ add_subdirectory(tools)

cad/cascade-compiler/pkg-descr

@@ -0,0 +1,11 @@
+Cascade is a novel solution to the problem that FPGAs take a long time to
+program, with complex programs taking hours to be compiled to run on FPGA.
+Cascade is a first just-in-time compiler for Verilog. Cascade executes code
+immediately in a software simulator, and performs compilation in the
+background. When compilation is finished, the code is moved into hardware, and
+from the user's perspective it simply gets faster over time. Cascade's ability
+to move code back and forth between software and hardware also makes it the
+first platform to provide generic support for the execution of unsynthesizable
+Verilog from hardware.
+
+WWW: https://github.com/vmware/cascade

cad/cascade-compiler/pkg-plist

@@ -0,0 +1,263 @@
+bin/cascade
+bin/cascade_slave
+bin/quartus_server
+bin/sw_fpga
+include/cascade.h
+include/cascade/cl/arg.h
+include/cascade/cl/arg_table.h
+include/cascade/cl/args.h
+include/cascade/cl/cl.h
+include/cascade/cl/comment_stream.h
+include/cascade/cl/dir_arg.h
+include/cascade/cl/file_arg.h
+include/cascade/cl/flag_arg.h
+include/cascade/cl/group.h
+include/cascade/cl/simple.h
+include/cascade/cl/singleton.h
+include/cascade/cl/str_arg.h
+include/cascade/common/bits.h
+include/cascade/common/cachestream.h
+include/cascade/common/fdstream.h
+include/cascade/common/incstream.h
+include/cascade/common/indstream.h
+include/cascade/common/log.h
+include/cascade/common/serializable.h
+include/cascade/common/sockserver.h
+include/cascade/common/sockstream.h
+include/cascade/common/system.h
+include/cascade/common/thread.h
+include/cascade/common/thread_pool.h
+include/cascade/common/tokenize.h
+include/cascade/common/undo_map.h
+include/cascade/common/undo_set.h
+include/cascade/common/undo_val.h
+include/cascade/common/undo_vector.h
+include/cascade/common/undoable.h
+include/cascade/common/uuid.h
+include/cascade/common/vector.h
+include/cascade/runtime/data_plane.h
+include/cascade/runtime/ids.h
+include/cascade/runtime/isolate.h
+include/cascade/runtime/module.h
+include/cascade/runtime/nullbuf.h
+include/cascade/runtime/runtime.h
+include/cascade/target/compiler.h
+include/cascade/target/compiler/local_compiler.h
+include/cascade/target/compiler/local_interface.h
+include/cascade/target/compiler/remote_compiler.h
+include/cascade/target/compiler/remote_interface.h
+include/cascade/target/compiler/rpc.h
+include/cascade/target/compiler/stub_core.h
+include/cascade/target/core.h
+include/cascade/target/core/avmm/avalon/avalon_compiler.h
+include/cascade/target/core/avmm/avalon/avalon_logic.h
+include/cascade/target/core/avmm/avalon/syncbuf.h
+include/cascade/target/core/avmm/avmm_compiler.h
+include/cascade/target/core/avmm/avmm_logic.h
+include/cascade/target/core/avmm/de10/de10_compiler.h
+include/cascade/target/core/avmm/de10/de10_config.h
+include/cascade/target/core/avmm/de10/de10_gpio.h
+include/cascade/target/core/avmm/de10/de10_led.h
+include/cascade/target/core/avmm/de10/de10_logic.h
+include/cascade/target/core/avmm/de10/de10_pad.h
+include/cascade/target/core/avmm/de10/hps.h
+include/cascade/target/core/avmm/de10/io.h
+include/cascade/target/core/avmm/de10/quartus_server.h
+include/cascade/target/core/avmm/de10/socal.h
+include/cascade/target/core/avmm/machinify.h
+include/cascade/target/core/avmm/rewrite.h
+include/cascade/target/core/avmm/text_mangle.h
+include/cascade/target/core/avmm/ulx3s/ulx3s_compiler.h
+include/cascade/target/core/avmm/ulx3s/ulx3s_logic.h
+include/cascade/target/core/avmm/var_table.h
+include/cascade/target/core/avmm/verilator/verilator_compiler.h
+include/cascade/target/core/avmm/verilator/verilator_logic.h
+include/cascade/target/core/common/interfacestream.h
+include/cascade/target/core/common/printf.h
+include/cascade/target/core/common/scanf.h
+include/cascade/target/core/proxy/proxy_compiler.h
+include/cascade/target/core/proxy/proxy_core.h
+include/cascade/target/core/sw/monitor.h
+include/cascade/target/core/sw/sw_clock.h
+include/cascade/target/core/sw/sw_compiler.h
+include/cascade/target/core/sw/sw_led.h
+include/cascade/target/core/sw/sw_logic.h
+include/cascade/target/core/sw/sw_pad.h
+include/cascade/target/core/sw/sw_reset.h
+include/cascade/target/core_compiler.h
+include/cascade/target/engine.h
+include/cascade/target/input.h
+include/cascade/target/interface.h
+include/cascade/target/state.h
+include/cascade/verilog/analyze/constant.h
+include/cascade/verilog/analyze/evaluate.h
+include/cascade/verilog/analyze/indices.h
+include/cascade/verilog/analyze/module_info.h
+include/cascade/verilog/analyze/navigate.h
+include/cascade/verilog/analyze/read_set.h
+include/cascade/verilog/analyze/resolve.h
+include/cascade/verilog/ast/ast.h
+include/cascade/verilog/ast/ast_fwd.h
+include/cascade/verilog/ast/types/always_construct.h
+include/cascade/verilog/ast/types/arg_assign.h
+include/cascade/verilog/ast/types/assign_statement.h
+include/cascade/verilog/ast/types/attr_spec.h
+include/cascade/verilog/ast/types/attributes.h
+include/cascade/verilog/ast/types/binary_expression.h
+include/cascade/verilog/ast/types/block_statement.h
+include/cascade/verilog/ast/types/blocking_assign.h
+include/cascade/verilog/ast/types/case_generate_construct.h
+include/cascade/verilog/ast/types/case_generate_item.h
+include/cascade/verilog/ast/types/case_item.h
+include/cascade/verilog/ast/types/case_statement.h
+include/cascade/verilog/ast/types/concatenation.h
+include/cascade/verilog/ast/types/conditional_expression.h
+include/cascade/verilog/ast/types/conditional_generate_construct.h
+include/cascade/verilog/ast/types/conditional_statement.h
+include/cascade/verilog/ast/types/construct.h
+include/cascade/verilog/ast/types/continuous_assign.h
+include/cascade/verilog/ast/types/debug_statement.h
+include/cascade/verilog/ast/types/declaration.h
+include/cascade/verilog/ast/types/event.h
+include/cascade/verilog/ast/types/event_control.h
+include/cascade/verilog/ast/types/expression.h
+include/cascade/verilog/ast/types/feof_expression.h
+include/cascade/verilog/ast/types/fflush_statement.h
+include/cascade/verilog/ast/types/finish_statement.h
+include/cascade/verilog/ast/types/fopen_expression.h
+include/cascade/verilog/ast/types/for_statement.h
+include/cascade/verilog/ast/types/fseek_statement.h
+include/cascade/verilog/ast/types/generate_block.h
+include/cascade/verilog/ast/types/generate_construct.h
+include/cascade/verilog/ast/types/generate_region.h
+include/cascade/verilog/ast/types/genvar_declaration.h
+include/cascade/verilog/ast/types/get_statement.h
+include/cascade/verilog/ast/types/id.h
+include/cascade/verilog/ast/types/identifier.h
+include/cascade/verilog/ast/types/if_generate_clause.h
+include/cascade/verilog/ast/types/if_generate_construct.h
+include/cascade/verilog/ast/types/initial_construct.h
+include/cascade/verilog/ast/types/instantiation.h
+include/cascade/verilog/ast/types/localparam_declaration.h
+include/cascade/verilog/ast/types/loop_generate_construct.h
+include/cascade/verilog/ast/types/loop_statement.h
+include/cascade/verilog/ast/types/macro.h
+include/cascade/verilog/ast/types/module_declaration.h
+include/cascade/verilog/ast/types/module_instantiation.h
+include/cascade/verilog/ast/types/module_item.h
+include/cascade/verilog/ast/types/multiple_concatenation.h
+include/cascade/verilog/ast/types/net_declaration.h
+include/cascade/verilog/ast/types/node.h
+include/cascade/verilog/ast/types/nonblocking_assign.h
+include/cascade/verilog/ast/types/number.h
+include/cascade/verilog/ast/types/par_block.h
+include/cascade/verilog/ast/types/parameter_declaration.h
+include/cascade/verilog/ast/types/port_declaration.h
+include/cascade/verilog/ast/types/primary.h
+include/cascade/verilog/ast/types/put_statement.h
+include/cascade/verilog/ast/types/range_expression.h
+include/cascade/verilog/ast/types/reg_declaration.h
+include/cascade/verilog/ast/types/repeat_statement.h
+include/cascade/verilog/ast/types/restart_statement.h
+include/cascade/verilog/ast/types/retarget_statement.h
+include/cascade/verilog/ast/types/save_statement.h
+include/cascade/verilog/ast/types/scope.h
+include/cascade/verilog/ast/types/seq_block.h
+include/cascade/verilog/ast/types/statement.h
+include/cascade/verilog/ast/types/string.h
+include/cascade/verilog/ast/types/system_task_enable_statement.h
+include/cascade/verilog/ast/types/timing_control.h
+include/cascade/verilog/ast/types/timing_control_statement.h
+include/cascade/verilog/ast/types/unary_expression.h
+include/cascade/verilog/ast/types/variable_assign.h
+include/cascade/verilog/ast/types/while_statement.h
+include/cascade/verilog/ast/visitors/builder.h
+include/cascade/verilog/ast/visitors/editor.h
+include/cascade/verilog/ast/visitors/rewriter.h
+include/cascade/verilog/ast/visitors/visitor.h
+include/cascade/verilog/build/ast_builder.h
+include/cascade/verilog/parse/lexer.h
+include/cascade/verilog/parse/parser.h
+include/cascade/verilog/print/color.h
+include/cascade/verilog/print/print.h
+include/cascade/verilog/print/printer.h
+include/cascade/verilog/print/term/term_printer.h
+include/cascade/verilog/print/text/text_printer.h
+include/cascade/verilog/program/elaborate.h
+include/cascade/verilog/program/inline.h
+include/cascade/verilog/program/program.h
+include/cascade/verilog/program/type_check.h
+include/cascade/verilog/transform/assign_unpack.h
+include/cascade/verilog/transform/block_flatten.h
+include/cascade/verilog/transform/constant_prop.h
+include/cascade/verilog/transform/control_merge.h
+include/cascade/verilog/transform/de_alias.h
+include/cascade/verilog/transform/dead_code_eliminate.h
+include/cascade/verilog/transform/delete_initial.h
+include/cascade/verilog/transform/event_expand.h
+include/cascade/verilog/transform/index_normalize.h
+include/cascade/verilog/transform/loop_unroll.h
+include/cascade_slave.h
+lib/libcascade.a
+%%DATADIR%%/avalon/avalon32_wrapper.v
+%%DATADIR%%/avalon/avalon64_wrapper.v
+%%DATADIR%%/de10/DE10_NANO_SOC_GHRD.sdc
+%%DATADIR%%/de10/DE10_NANO_SoC_GHRD.qpf
+%%DATADIR%%/de10/DE10_NANO_SoC_GHRD.qsf
+%%DATADIR%%/de10/DE10_NANO_SoC_GHRD.v
+%%DATADIR%%/de10/DE10_NANO_SoC_GHRD_assignment_defaults.qdf
+%%DATADIR%%/de10/assemble_de10.sh
+%%DATADIR%%/de10/build_de10.sh
+%%DATADIR%%/de10/generate_hps_qsys_header.sh
+%%DATADIR%%/de10/hps_common_board_info.xml
+%%DATADIR%%/de10/hps_sdram_p0_summary.csv
+%%DATADIR%%/de10/ip/altsource_probe/hps_reset.qip
+%%DATADIR%%/de10/ip/altsource_probe/hps_reset.v
+%%DATADIR%%/de10/ip/altsource_probe/hps_reset_bb.v
+%%DATADIR%%/de10/program_logic_hw.tcl
+%%DATADIR%%/de10/soc_system.dtb
+%%DATADIR%%/de10/soc_system.dts
+%%DATADIR%%/de10/soc_system.qsys
+%%DATADIR%%/de10/soc_system_board_info.xml
+%%DATADIR%%/de10/sof2rbf.cof
+%%DATADIR%%/de10/software/spl_bsp/Makefile
+%%DATADIR%%/de10/software/spl_bsp/generated/build.h
+%%DATADIR%%/de10/software/spl_bsp/generated/iocsr_config_cyclone5.c
+%%DATADIR%%/de10/software/spl_bsp/generated/iocsr_config_cyclone5.h
+%%DATADIR%%/de10/software/spl_bsp/generated/pinmux_config.h
+%%DATADIR%%/de10/software/spl_bsp/generated/pinmux_config_cyclone5.c
+%%DATADIR%%/de10/software/spl_bsp/generated/pll_config.h
+%%DATADIR%%/de10/software/spl_bsp/generated/reset_config.h
+%%DATADIR%%/de10/software/spl_bsp/generated/sdram/sdram_config.h
+%%DATADIR%%/de10/software/spl_bsp/preloader-mkpimage.bin
+%%DATADIR%%/de10/software/spl_bsp/preloader.ds
+%%DATADIR%%/de10/software/spl_bsp/settings.bsp
+%%DATADIR%%/de10/software/spl_bsp/u-boot.img
+%%DATADIR%%/de10/software/spl_bsp/uboot.ds
+%%DATADIR%%/march/de10.v
+%%DATADIR%%/march/regression/avalon32.v
+%%DATADIR%%/march/regression/avalon64.v
+%%DATADIR%%/march/regression/concurrent.v
+%%DATADIR%%/march/regression/jit.v
+%%DATADIR%%/march/regression/minimal.v
+%%DATADIR%%/march/regression/no_inline.v
+%%DATADIR%%/march/regression/remote.v
+%%DATADIR%%/march/regression/verilator32.v
+%%DATADIR%%/march/regression/verilator64.v
+%%DATADIR%%/march/sw.v
+%%DATADIR%%/march/ulx3s.v
+%%DATADIR%%/stdlib/iterator.v
+%%DATADIR%%/stdlib/memory.v
+%%DATADIR%%/stdlib/stdlib.v
+%%DATADIR%%/ulx3s/build_ulx3s_32.sh
+%%DATADIR%%/ulx3s/harness.v
+%%DATADIR%%/ulx3s/root32.v
+%%DATADIR%%/ulx3s/uart.v
+%%DATADIR%%/ulx3s/uart_rx.v
+%%DATADIR%%/ulx3s/uart_tx.v
+%%DATADIR%%/ulx3s/ulx3s_v20.lpf
+%%DATADIR%%/verilator/build_verilator_32.sh
+%%DATADIR%%/verilator/build_verilator_64.sh
+%%DATADIR%%/verilator/fake_main.cpp
+%%DATADIR%%/verilator/harness_32.cpp
+%%DATADIR%%/verilator/harness_64.cpp