Commit Graph

26 Commits

Author SHA1 Message Date
Vanilla I. Shu
9f233704f3 gEDA electronic schematic capture tools
Submitted by:	bruno.schwander@technologist.com
2001-04-07 00:20:37 +00:00
Vanilla I. Shu
1c640af553 gEDA electronic schematic capture tools
Submitted by:	bruno.schwander@technologist.com
2001-04-07 00:19:08 +00:00
Vanilla I. Shu
ad3b4801e5 geda-symbols is the basic component of geda package.
Submitted byu.schwander@technologist.com
2001-04-07 00:17:32 +00:00
Vanilla I. Shu
1071e87cec libgeda is a a base library common to all the gEDA tools
Submitted by:	bruno.schwander@technologist.com
2001-04-07 00:09:57 +00:00
Ying-Chieh Liao
bb9c476eb6 add vipec
ViPEC is a powerful tool for the analysis of high frequency, linear electrical networks
2001-04-03 05:30:51 +00:00
Akinori MUSHA
0aaeab888e Add oregano, schematic capture and simulation of electrical circuits.
PR:		ports/25202
Submitted by:	Anders Andersson <anders@codefactory.se>
2001-03-07 11:00:31 +00:00
Ying-Chieh Liao
7bf8e1d6ec add iverilog, a Verilog simulation and synthesis tool 2001-02-13 11:02:15 +00:00
Greg Lehey
9635aa5387 SCEPTRE (System for Circuit Evaluation and Prediction of Transient
Radiation Effects) is a general purpose circuit analysis program which
provides all three major analyses, AC, DC, and transient analysis, on
either linear or nonlinear networks.  It employs a free-form input
language and state variable methods to simulate problems of interest
to electrical engineers.

Requested-by:	"Pedro F. Giffuni" <pfg1+@pitt.edu>
2001-02-11 06:58:11 +00:00
SADA Kenji
bf66fc5159 Activate Electric.
PR:		ports/18380
Submitted by:	Mario Sergio Fujikawa Ferreira <lioux@linf.unb.br>
2000-07-30 07:14:47 +00:00
Ade Lovett
51e78bed9c Add PISCES, a two-dimensional device simulator which includes
models for surface mobility, impact ionization and photo-generation.
Quasi-three-dimensional simulation of cylindrically-symmetric devices is
also supported.

PR:		14686
Submitted by:	Gianlorenzo Masini <masini@uniroma3.it>
2000-05-03 14:59:53 +00:00
Steve Price
55faf4942d cider version 1b1
A mixed-level circuit and device simulator (includes SPICE3).

PR:		15462
Submitted by:	AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
1999-12-25 15:40:48 +00:00
Thomas Gellekum
617acea261 New port QCad, a 2D-CAD program. Uses Qt-2. 1999-12-22 10:40:56 +00:00
David E. O'Brien
fe1e09a6cc Change Id->FreeBSD. 1999-08-25 04:58:03 +00:00
Steve Price
f90dfc50e8 Activate the tkgate port. 1999-06-06 17:12:34 +00:00
Satoshi Asami
75e0c6c35e Sort entries. In particular, "large", "medium", "small" sort in this order,
dispite their meanings.  (Sometimes we're too smart for computers. :)

Found by:	sorting ports/INDEX by "sort -t '|' +1 -2"

(Note: the whole "x11" category appears at the end with the above sort
 command, but I'll leave that the way it is for now -- "ls" shows it
 before other x11-* entries.)
1998-12-07 02:22:12 +00:00
Vanilla I. Shu
7c5cb28323 Activate geda. 1998-12-06 14:13:23 +00:00
Guy Helmer
2c26d9e848 Enable sis, a new circuit emulator port. 1998-07-01 15:40:47 +00:00
Matthew Hunt
6ae8c69099 Activate xcircuit. 1998-05-18 04:21:53 +00:00
Thomas Gellekum
7ff48bbb2e Activate kaskade. 1997-11-17 10:53:52 +00:00
Satoshi Asami
9817133d7c Add felt. 1997-01-15 07:49:06 +00:00
David E. O'Brien
405dd2c62f Turn on mars and lprps 1996-11-25 01:24:47 +00:00
Thomas Gellekum
115800797c Add spice. 1996-05-23 08:29:27 +00:00
Satoshi Asami
750d5b551b Add chipmunk, convert to new format along the way. 1995-08-25 10:06:06 +00:00
Satoshi Asami
c9dc84a522 Clean up subdir Makefiles. They now all look like this:
=====
# Id line
#
# RESTRICTED: restricted_port_1 (comment1)
# RESTRICTED: restricted_port_2 (comment2)
#
# BROKEN: broken_port_3 (comment3)
# BROKEN: broken_port_4 (comment4)
# BROKEN: broken_port_5 (comment5)
#

SUBDIR= good_port_1 good_port_2 ...
=====

Basically, the idea is to make it easy to find restricted or broken
ports by doing a "grep".
1995-05-14 03:30:07 +00:00
Jordan K. Hubbard
7c903ca232 Alphabetize. 1995-01-13 14:00:40 +00:00
Jordan K. Hubbard
5e89d8e7e6 New cad group 1995-01-13 11:10:43 +00:00