52 lines
967 B
Systemverilog
52 lines
967 B
Systemverilog
module vdp
|
|
(input i_clk,
|
|
input i_rst,
|
|
output o_r,
|
|
output o_g,
|
|
output o_b,
|
|
output o_hsync,
|
|
output o_vsync);
|
|
|
|
wire [12:0] cg_addr;
|
|
wire [15:0] cg_data;
|
|
wire [10:0] row;
|
|
wire [10:0] col;
|
|
wire hsync;
|
|
wire vsync;
|
|
wire de;
|
|
|
|
assign o_hsync = ~hsync;
|
|
assign o_vsync = ~vsync;
|
|
|
|
vga_timing_gen vga_timing_gen_inst
|
|
(.i_clk(i_clk),
|
|
.i_rst(i_rst),
|
|
.o_hsync(hsync),
|
|
.o_vsync(vsync),
|
|
.o_row(row),
|
|
.o_col(col),
|
|
.o_de(de));
|
|
|
|
chargen chargen_inst
|
|
(.i_clk(i_clk),
|
|
.i_rst(i_rst),
|
|
.i_row(row),
|
|
.i_col(col),
|
|
.i_de(de),
|
|
.i_ram_data(cg_data),
|
|
.o_ram_addr(cg_addr),
|
|
.o_r(o_r),
|
|
.o_g(o_g),
|
|
.o_b(o_b));
|
|
|
|
charram charram_inst
|
|
(.i_clk(i_clk),
|
|
.i_rst(i_rst),
|
|
.i_cpu_addr(13'd0),
|
|
.i_cpu_data(16'd0),
|
|
.i_cpu_we(1'b0),
|
|
.i_gen_addr(cg_addr),
|
|
.o_gen_data(cg_data));
|
|
|
|
endmodule
|