39 lines
893 B
Verilog
39 lines
893 B
Verilog
module testbram
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(input i_clk,
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input i_rst,
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input i_dir,
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input [1:0] i_act,
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input [31:0] i_addr,
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input [31:0] i_data,
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output reg [31:0] o_data,
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output o_we);
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(* ram_style = "block" *)
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reg [31:0] sram [4095:0];
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(* ram_style = "block" *)
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reg [31:0] srom [4095:0];
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wire use_ram = (i_addr >= 32'h00004000) && (i_addr < 32'h00008000);
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wire use_rom = (i_addr < 32'h00004000);
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assign o_we = ~i_dir && (i_act != 2'b00);
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// WRITE - simplest possible
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always @(posedge i_clk) begin
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if (i_dir && use_ram)
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sram[i_addr[13:2]] <= i_data;
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end
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// READ - simplest possible
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always @(posedge i_clk) begin
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if (use_ram)
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o_data <= sram[i_addr[13:2]];
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else if (use_rom)
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o_data <= srom[i_addr[13:2]];
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else
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o_data <= 32'h0;
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end
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endmodule
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