40 lines
720 B
Verilog
40 lines
720 B
Verilog
module sequencer
|
|
(input i_clk,
|
|
input i_rst,
|
|
input [8:0] i_a,
|
|
input [1:0] i_op,
|
|
input i_cc,
|
|
input i_halt,
|
|
output [8:0] o_y);
|
|
|
|
wire [8:0] inc_pc;
|
|
wire [8:0] next_pc;
|
|
wire [8:0] next_ra;
|
|
|
|
reg [8:0] pc;
|
|
reg [8:0] ra;
|
|
|
|
assign inc_pc = pc + 1;
|
|
|
|
assign next_pc = (i_halt) ? pc :
|
|
(i_op[0] & i_cc) ? i_a :
|
|
(i_op[1] & ~i_op[0] & i_cc) ? ra :
|
|
inc_pc;
|
|
|
|
assign next_ra = (i_op == 2'b11 && !i_halt) ? inc_pc :
|
|
(i_op == 2'b10 && !i_halt) ? 0 :
|
|
ra;
|
|
|
|
assign o_y = next_pc;
|
|
|
|
always @(posedge i_clk, posedge i_rst) begin
|
|
if (i_rst) begin
|
|
pc <= 9'h1F8;
|
|
ra <= 0;
|
|
end else begin
|
|
pc <= next_pc;
|
|
ra <= next_ra;
|
|
end
|
|
end
|
|
endmodule
|