43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
module bus_interface
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(input i_clk,
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input i_rst,
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input [1:0] i_act,
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input i_dir,
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input [31:0] i_cpu_data,
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input [31:0] i_cpu_addr,
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output [31:0] o_cpu_data,
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output o_cpu_we,
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output o_rwait,
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output o_wwait,
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/* Wishbone */
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input i_ack,
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input [31:0] i_dat,
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output [31:0] o_dat,
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output [31:0] o_adr,
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output o_we,
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output o_cyc,
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output o_stb,
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output [1:0] o_sel);
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wire [3:0] sel;
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wire err;
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assign {err, sel} = (i_act == 0) ? 5b'00000 :
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(i_act == 1 && i_cpu_addr[1:0] == 2'b00) ? 5b'00001 :
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(i_act == 1 && i_cpu_addr[1:0] == 2'b01) ? 5b'00010 :
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(i_act == 1 && i_cpu_addr[1:0] == 2'b10) ? 5b'00100 :
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(i_act == 1 && i_cpu_addr[1:0] == 2'b11) ? 5b'01000 :
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(i_act == 2 && i_cpu_addr[1:0] == 2'b00) ? 5b'00011 :
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(i_act == 2 && i_cpu_addr[1:0] == 2'b10) ? 5b'01100 :
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(i_act == 3 && i_cpu_addr[1:0] == 2'b00) ? 5b'01111 :
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5'b10000;
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assign o_sel = sel;
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always @(posedge i_clk, posedge i_rst) begin
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if (i_rst) begin
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end else begin
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end
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end
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endmodule
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