module bus_interface
  (input	 i_clk,
   input	 i_rst,
   input [1:0]	 i_act,
   input	 i_dir,
   input [31:0]	 i_cpu_data,
   input [31:0]	 i_cpu_addr,
   output [31:0] o_cpu_data,
   output	 o_cpu_we,
   output	 o_rwait,
   output	 o_wwait,

   /* Wishbone */
   input	 i_ack,
   input [31:0]	 i_dat,
   output [31:0] o_dat,
   output [31:0] o_adr,
   output	 o_we,
   output	 o_cyc,
   output	 o_stb,
   output [1:0]	 o_sel);

   wire [3:0] sel;
   wire	      err;

   assign {err, sel} = (i_act == 0) ? 5b'00000 :
		       (i_act == 1 && i_cpu_addr[1:0] == 2'b00) ? 5b'00001 :
		       (i_act == 1 && i_cpu_addr[1:0] == 2'b01) ? 5b'00010 :
		       (i_act == 1 && i_cpu_addr[1:0] == 2'b10) ? 5b'00100 :
		       (i_act == 1 && i_cpu_addr[1:0] == 2'b11) ? 5b'01000 :
		       (i_act == 2 && i_cpu_addr[1:0] == 2'b00) ? 5b'00011 :
		       (i_act == 2 && i_cpu_addr[1:0] == 2'b10) ? 5b'01100 :
		       (i_act == 3 && i_cpu_addr[1:0] == 2'b00) ? 5b'01111 :
		       5'b10000;
   assign o_sel = sel;
   
   always @(posedge i_clk, posedge i_rst) begin
      if (i_rst) begin
      end else begin
      end
   end
endmodule