50 lines
1.1 KiB
Makefile
50 lines
1.1 KiB
Makefile
PROJECT = cpu
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BOARD = tangnano20k
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FAMILY = GW2A-18C
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DEVICE = GW2AR-LV18QN88C8/I7
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# Source files
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VERILOG_SRC = cpu.v register_file.v sequencer.v alu.v sram_srom.v
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TOP_MODULE = cpu
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# Constraint file
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CST = tangnano20k.cst
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# Synthesis
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$(PROJECT).json: $(VERILOG_SRC)
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yosys -p "read_verilog $(VERILOG_SRC); \
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synth_gowin -top $(TOP_MODULE) -json $@"
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# Place & Route
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$(PROJECT)_pnr.json: $(PROJECT).json
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nextpnr-gowin --json $< \
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--write $@ \
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--device $(DEVICE) \
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--family $(FAMILY) \
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--cst $(CST)
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# Generate bitstream
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$(PROJECT).fs: $(PROJECT)_pnr.json
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gowin_pack -d $(FAMILY) -o $@ $
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# Program FPGA
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load: $(PROJECT).fs
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openFPGALoader -b $(BOARD) $
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# Flash to FPGA
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flash: $(PROJECT).fs
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openFPGALoader -b $(BOARD) -f $
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# Clean
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clean:
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rm -f $(PROJECT).json $(PROJECT)_pnr.json $(PROJECT).fs
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tsim:
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./uasm.py ucode.src
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customasm -f readmemh,width:32 hope.asm -o sromr.hex
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./revhex.py sromr.hex srom.hex
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iverilog -o cpu_sim cpu_tb2.v cpu.v register_file.v alu.v sequencer.v sram_srom.v
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./cpu_sim|more
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.PHONY: load flash clean tsim
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