2021-02-05 23:59:31 -05:00
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#ifndef __RigState_h__
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#define __RigState_h__
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2021-02-07 00:45:19 -05:00
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#include <Arduino.h>
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2021-02-09 23:58:07 -05:00
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#define UBITX_VFOA_UPDATE 0x00000001
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#define UBITX_VFOB_UPDATE 0x00000002
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#define UBITX_RIT_UPDATE 0x00000004
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#define UBITX_XIT_UPDATE 0x00000008
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#define UBITX_FLAGS_UPDATE 0x00000010
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#define UBITX_VFOB_FLAG 0x00000001
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#define UBITX_SPLIT_FLAG 0x00000002
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#define UBITX_RIT_FLAG 0x00000004
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#define UBITX_XIT_FLAG 0x00000008
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#define UBITX_CW_FLAG 0x00000010
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#define UBITX_USB_FLAG 0x00000020
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#define UBITX_TX_FLAG 0x00000040
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struct UBitxRigState {
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uint32_t header = 0;
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uint32_t vfo[2];
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int32_t rit;
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int32_t xit;
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uint32_t flags = 0;
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};
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2021-02-11 23:00:24 -05:00
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/**********************************************************************/
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2021-02-14 01:35:38 -05:00
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// NEW IMPLEMENTATION
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2021-02-11 23:00:24 -05:00
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struct Field {
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bool dirty;
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uint32_t data;
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2021-02-14 01:35:38 -05:00
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/*
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template<typename STREAM> void writeChanges() {
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if (dirty) {
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STREAM().write(id);
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STREAM().write((byte*)&data, sizeof(T));
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}
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}
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template<typename STREAM> int read() {
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size_t len = 0;
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byte* ptr = (byte*)&data;
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while (STREAM().available() && len < sizeof(T)) {
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ptr[len++] = STREAM().read();
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}
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return len;
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}
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*/
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inline void merge(Field& f) {
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if (dirty) {
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f.data = data;
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f.dirty = true;
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} else if (f.dirty) {
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data = f.data;
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dirty = true;
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}
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}
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inline void markClean() { dirty = false; }
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};
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2021-02-14 01:35:38 -05:00
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#define WIREBUS_NONE 0
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#define WIREBUS_VFO_A 1
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#define WIREBUS_VFO_B 2
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#define WIREBUS_RIT_OFS 3
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#define WIREBUS_XIT_OFS 4
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#define WIREBUS_FLAGS 5
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#define WIREBUS_NUM_FIELDS 6
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typedef bool (*readfunc)(uint32_t*);
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typedef void (*writefunc)(uint32_t);
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struct RigState {
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Field field[WIREBUS_NUM_FIELDS];
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readfunc readFunc[WIREBUS_NUM_FIELDS];
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writefunc writeFunc[WIREBUS_NUM_FIELDS;
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int numDirty;
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void begin();
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void update();
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/*!
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* @brief Read in the specified (by index) external value, and use
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* it to update the rig state.
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*/
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inline bool read(byte i) {
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return readFunc[i](&field[i].data);
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}
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/*!
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* @brief Use the specified (vy index) rig state field to update the
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* external value.
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*/
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inline void write(byte i) {
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writeFunc[i](field[i].data);
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}
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inline unsigned getFreqA() const { return field[WIREBUS_VFO_A].data; }
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inline unsigned getFreqB() const { return field[WIREBUS_VFO_B].data; }
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inline int getRIT() const { return int(field[WIREBUS_VFO_A].data); }
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inline int getXIT() const { return int(field[WIREBUS_VFO_B].data); }
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inline bool isVFOA() const { return (field[WIREBUS_FLAGS].data & UBITX_VFOB_FLAG) != UBITX_VFOB_FLAG; }
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inline bool isVFOB() const { return (field[WIREBUS_FLAGS].data & UBITX_VFOB_FLAG) == UBITX_VFOB_FLAG; }
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inline bool isSplit() const { return (field[WIREBUS_FLAGS].data & UBITX_SPLIT_FLAG) == UBITX_SPLIT_FLAG; }
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inline bool isRITOn() const { return (field[WIREBUS_FLAGS].data & UBITX_RIT_FLAG) == UBITX_RIT_FLAG; }
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inline bool isXITOn() const { return (field[WIREBUS_FLAGS].data & UBITX_XIT_FLAG) == UBITX_XIT_FLAG; }
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inline bool isCW() const { return (field[WIREBUS_FLAGS].data & UBITX_CW_FLAG) == UBITX_CW_FLAG; }
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inline bool isLSB() const { return (field[WIREBUS_FLAGS].data & UBITX_USB_FLAG) != UBITX_USB_FLAG; }
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inline bool isUSB() const { return (field[WIREBUS_FLAGS].data & UBITX_USB_FLAG) == UBITX_USB_FLAG; }
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/*
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inline size_t sizeOfWrite() {
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size_t size = 0;
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size += vfoA.sizeOfWrite();
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size += vfoB.sizeOfWrite();
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size += rit.sizeOfWrite();
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size += xit.sizeOfWrite();
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size += flags.sizeOfWrite();
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return size;
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}
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template<typename STREAM> void writeChanges() {
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vfoA.writeChanges<STREAM>();
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vfoB.writeChanges<STREAM>();
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rit.writeChanges<STREAM>();
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xit.writeChanges<STREAM>();
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flags.writeChanges<STREAM>();
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}
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template<typename STREAM> void readChanges(size_t size) {
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size_t len = 0;
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while (STREAM().available() && len < size) {
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switch(STREAM().read()) {
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case 0:
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len += vfoA.read<STREAM>();
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break;
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case 1:
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len += vfoB.read<STREAM>();
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break;
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case 2:
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len += rit.read<STREAM>();
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break;
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case 3:
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len += xit.read<STREAM>();
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break;
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case 4:
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len += flags.read<STREAM>();
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break;
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default:
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;
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}
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}
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}
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inline void merge(RigState& r) {
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vfoA.merge(r.vfoA);
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vfoB.merge(r.vfoB);
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rit.merge(r.rit);
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xit.merge(r.xit);
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flags.merge(r.flags);
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}
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inline void markClean(RigState& r) {
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vfoA.markClean();
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vfoB.markClean();
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rit.markClean();
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xit.markClean();
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flags.markClean();
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}
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2021-02-14 01:35:38 -05:00
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*/
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};
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2021-02-14 01:35:38 -05:00
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#ifdef TEENSYDUINO
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extern RigState inState; // the state as received from the Raduino
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extern RigState outState; // the state as commanded via CAT
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#else
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extern RigState rigState;
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#endif
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2021-02-11 23:00:24 -05:00
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/*
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Protocol discussion:
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- I2C master: Raduino
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- I2C slave: TeensyDSP
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Raduino state:
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- Baseline uBITX variables
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- I2C buffer
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- On I2C transmit: make updates based on current variables
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- On I2C receive:
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- Update based on received I2C responses
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- Update associated variables
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TeensyDSP state:
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- CAT buffer
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- Used to receive command from CAT (when commands arrive via Serial)
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- Used to transmit state to Raduino (when requested via Wire1)
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- Raduino buffer
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- Used to receive state from Raduino (when received via Wire1)
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- Used to transmit responses to CAT (over Serial)
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- Questions
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- How can these be synchronized?
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- At the tail end of an I2C request handler. Before sending the response to the Raduino via I2C:
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- Copy updated CAT buffer items to the Raduino buffer.
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- Copy updated Raduino buffer items to the CAT buffer.
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- In the case of conflicts, CAT wins.
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- Transmit the CAT buffer state to the Raduino.
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- TeensyDSP updates 'outgoing' state based on CAT inputs.
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- Make change to data.
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- Mark data as dirty, if different than incoming state.
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- When requested, Teensy DSP sends 'outgoing' state to Raduino.
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- Send dirty data over I2C.
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- Mark data as clean.
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*/
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2021-02-05 23:59:31 -05:00
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#endif
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