Original submission from Alessandro De Laurenzis, who takes MAINTAINER --
thanks!
Additional work from sthen@ and myself, ok sthen@
ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
f919501846