bcallah f919501846 Import cad/abc, a system for sequential logic synthesis and verification.
Original submission from Alessandro De Laurenzis, who takes MAINTAINER --
thanks!

Additional work from sthen@ and myself, ok sthen@

ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
2018-08-08 15:24:47 +00:00

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@comment $OpenBSD: PLIST,v 1.1.1.1 2018/08/08 15:24:47 bcallah Exp $
@bin bin/abc