ab10d0eb39
- [Sparc] Fix addressing mode when using 64-bit values in inline assembly - [Sparc] Use synthetic instruction clr to zero register instead of sethi from Brad (maintainer)
23 lines
914 B
Plaintext
23 lines
914 B
Plaintext
$OpenBSD: patch-lib_Target_Sparc_SparcISelDAGToDAG_cpp,v 1.3 2018/04/28 15:04:29 ajacoutot Exp $
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[Sparc] Fix addressing mode when using 64-bit values in inline assembly
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Summary:
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If a 64-bit register is used as an operand in inline assembly together
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with a memory reference, the memory addressing will be wrong. The
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addressing will be a single reg, instead of reg+reg or reg+imm. This
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will generate a bad offset value or an exception in printMemOperand().
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Index: lib/Target/Sparc/SparcISelDAGToDAG.cpp
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--- lib/Target/Sparc/SparcISelDAGToDAG.cpp.orig
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+++ lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@@ -311,6 +311,8 @@ bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
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if (!Changed)
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return false;
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+ SelectInlineAsmMemoryOperands(AsmNodeOperands, SDLoc(N));
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+
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SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
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CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
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New->setNodeId(-1);
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