114 lines
5.0 KiB
Plaintext
114 lines
5.0 KiB
Plaintext
Make sure that we really don't emit quad-precision unless the
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"hard-quad-float" feature is available
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Index: lib/Target/Sparc/SparcInstrInfo.td
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--- lib/Target/Sparc/SparcInstrInfo.td.orig
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+++ lib/Target/Sparc/SparcInstrInfo.td
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@@ -487,6 +487,27 @@ let Uses = [ICC], usesCustomInserter = 1 in {
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[(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
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}
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+let Uses = [ICC], usesCustomInserter = 1 in {
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+ def SELECT_CC_Int_XCC
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+ : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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+ "; SELECT_CC_Int_XCC PSEUDO!",
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+ [(set i32:$dst, (SPselectxcc i32:$T, i32:$F, imm:$Cond))]>;
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+ def SELECT_CC_FP_XCC
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+ : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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+ "; SELECT_CC_FP_XCC PSEUDO!",
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+ [(set f32:$dst, (SPselectxcc f32:$T, f32:$F, imm:$Cond))]>;
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+
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+ def SELECT_CC_DFP_XCC
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+ : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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+ "; SELECT_CC_DFP_XCC PSEUDO!",
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+ [(set f64:$dst, (SPselectxcc f64:$T, f64:$F, imm:$Cond))]>;
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+
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+ def SELECT_CC_QFP_XCC
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+ : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
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+ "; SELECT_CC_QFP_XCC PSEUDO!",
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+ [(set f128:$dst, (SPselectxcc f128:$T, f128:$F, imm:$Cond))]>;
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+}
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+
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let usesCustomInserter = 1, Uses = [FCC0] in {
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def SELECT_CC_Int_FCC
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@@ -1418,12 +1439,12 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
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(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
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"fmovd$cond %icc, $rs2, $rd",
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[(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
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+ let Predicates = [HasV9, HasHardQuad] in
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def FMOVQ_ICC
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: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovq$cond %icc, $rs2, $rd",
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- [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
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- Requires<[HasHardQuad]>;
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+ [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
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}
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let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
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@@ -1437,12 +1458,12 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in
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(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
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"fmovd$cond %fcc0, $rs2, $rd",
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[(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
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+ let Predicates = [HasV9, HasHardQuad] in
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def FMOVQ_FCC
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: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovq$cond %fcc0, $rs2, $rd",
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- [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
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- Requires<[HasHardQuad]>;
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+ [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
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}
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}
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@@ -1452,28 +1473,28 @@ let Predicates = [HasV9] in {
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def FMOVD : F3_3u<2, 0b110100, 0b000000010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fmovd $rs2, $rd", []>;
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+ let Predicates = [HasV9, HasHardQuad] in
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def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
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- "fmovq $rs2, $rd", []>,
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- Requires<[HasHardQuad]>;
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+ "fmovq $rs2, $rd", []>;
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def FNEGD : F3_3u<2, 0b110100, 0b000000110,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fnegd $rs2, $rd",
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[(set f64:$rd, (fneg f64:$rs2))]>;
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+ let Predicates = [HasV9, HasHardQuad] in
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def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
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"fnegq $rs2, $rd",
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- [(set f128:$rd, (fneg f128:$rs2))]>,
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- Requires<[HasHardQuad]>;
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+ [(set f128:$rd, (fneg f128:$rs2))]>;
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def FABSD : F3_3u<2, 0b110100, 0b000001010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fabsd $rs2, $rd",
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[(set f64:$rd, (fabs f64:$rs2))]>;
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+ let Predicates = [HasV9, HasHardQuad] in
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def FABSQ : F3_3u<2, 0b110100, 0b000001011,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
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"fabsq $rs2, $rd",
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- [(set f128:$rd, (fabs f128:$rs2))]>,
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- Requires<[HasHardQuad]>;
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+ [(set f128:$rd, (fabs f128:$rs2))]>;
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}
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// Floating-point compare instruction with %fcc0-%fcc3.
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@@ -1520,11 +1541,11 @@ let Predicates = [HasV9] in {
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: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
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(ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
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"fmovd$cond $opf_cc, $rs2, $rd", []>;
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+ let Predicates = [HasV9, HasHardQuad] in
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def V9FMOVQ_FCC
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: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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- "fmovq$cond $opf_cc, $rs2, $rd", []>,
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- Requires<[HasHardQuad]>;
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+ "fmovq$cond $opf_cc, $rs2, $rd", []>;
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} // Constraints = "$f = $rd", ...
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} // let Predicates = [hasV9]
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