38 lines
848 B
Makefile
38 lines
848 B
Makefile
# $OpenBSD: Makefile,v 1.17 2017/10/05 08:58:10 bentley Exp $
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COMMENT= Verilog simulation and synthesis tool
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V= 10.2
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DISTNAME= verilog-$V
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PKGNAME= iverilog-$V
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CATEGORIES= lang devel
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HOMEPAGE= http://iverilog.icarus.com/
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# GPLv2+
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PERMIT_PACKAGE_CDROM= Yes
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MASTER_SITES= ftp://ftp.icarus.com/pub/eda/verilog/v10/
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WANTLIB += c m pthread readline ${COMPILER_LIBCXX} termcap z
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USE_GMAKE= Yes
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BUILD_DEPENDS= devel/bison
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YACC= bison
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CONFIGURE_STYLE= gnu
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CONFIGURE_ARGS+= --disable-suffix
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CFLAGS+= -fPIC
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VVP_DOCS= README.txt opcodes.txt
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DOC_DIR= ${PREFIX}/share/doc/iverilog
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post-install:
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${INSTALL_DATA_DIR} ${DOC_DIR}/{ivlpp,vvp}
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${INSTALL_DATA} ${WRKSRC}/*.txt ${DOC_DIR}
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${INSTALL_DATA} ${WRKSRC}/vvp/{README,opcodes}.txt ${DOC_DIR}/vvp/
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${INSTALL_DATA} ${WRKSRC}/ivlpp/ivlpp.txt ${DOC_DIR}/ivlpp/
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.include <bsd.port.mk>
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