af04cfdc9c
- Add retguard for octeon/mips64. - Move the hashed __retguard_* symbols into individual sections and mark them as COMDATs so that the linker can individually discard them, instead of just ignoring duplicate symbols but keep the (duplicate) space. from Brad
62 lines
3.0 KiB
Plaintext
62 lines
3.0 KiB
Plaintext
$OpenBSD: patch-lib_Target_Mips_MipsInstrInfo_td,v 1.2 2020/01/07 22:59:43 jca Exp $
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- Add retguard for octeon/mips64.
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- Implement SGE pseudo-instructions. Needed when building libcrypto.
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Index: lib/Target/Mips/MipsInstrInfo.td
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--- lib/Target/Mips/MipsInstrInfo.td.orig
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+++ lib/Target/Mips/MipsInstrInfo.td
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@@ -2022,6 +2022,31 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst)
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def LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst),
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(ins GPR32Opnd:$src, brtarget:$tgt), []>;
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+// Pseudo instructions used by retguard. In order to calculste the PC
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+// for PIC code, we use a pair of pseudos to get the function address
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+// into T9, which is normally used to hold this value but is trashed
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+// by function epilogue.
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+let isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
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+
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+ // Use BAL to get the PC into RA, then calculate the address of the
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+ // current function and save this value in $rd. $rs and $rt are used
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+ // as scratch registers and are trashed by this pseudo. $tgt is the
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+ // symbol to branch to when calling BAL.
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+ let Size = 32 in {
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+ def RETGUARD_GET_FUNCTION_ADDR: PseudoSE<(outs GPR64:$rd),
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+ (ins GPR64:$rs, GPR64:$rt, brtarget:$tgt), []>;
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+ }
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+
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+ // Emit the symbol used for $tgt in RETGUARD_GET_FUNCTION_ADDR. We
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+ // emit this symbol immediately before the usual function return, with
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+ // the effect that the BAL branches to an immediate return and resumes
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+ // execution through the rest of the RETGUARD epilogue. We pair BAL
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+ // with RET to satisfy return branch predictors.
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+ let Size = 0 in {
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+ def RETGUARD_EMIT_SYMBOL: PseudoSE<(outs), (ins brtarget:$tgt), []>;
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+ }
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+}
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+
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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@@ -3007,6 +3032,20 @@ def LDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
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def SDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
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(ins mem_simm16:$addr), "sd $rt, $addr">,
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ISA_MIPS1_NOT_MIPS3;
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+
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+def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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+ "sge\t$rd, $rs, $rt">;
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+def SGEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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+ "sgeu\t$rd, $rs, $rt">;
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+def SGEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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+ (ins GPR32Opnd:$rs, simm32_relaxed:$imm),
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+ "sge\t$rd, $rs, $imm">, GPR_32;
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+def SGEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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+ (ins GPR32Opnd:$rs, simm32_relaxed:$imm),
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+ "sgeu\t$rd, $rs, $imm">, GPR_32;
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+
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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