Original submission from Alessandro De Laurenzis, who takes MAINTAINER -- thanks! Additional work from sthen@ and myself, ok sthen@ ABC is a growing software system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. ABC combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.
32 lines
743 B
Makefile
32 lines
743 B
Makefile
# $OpenBSD: Makefile,v 1.1.1.1 2018/08/08 15:24:47 bcallah Exp $
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COMMENT = system for sequential logic synthesis and verification
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DISTNAME = abc-1.01.20180722
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CATEGORIES = cad
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GH_ACCOUNT = berkeley-abc
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GH_PROJECT = abc
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GH_COMMIT = ae6716b064c842f45109a88e84dca71fe4cc311f
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HOMEPAGE = https://people.eecs.berkeley.edu/~alanmi/abc
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MAINTAINER = Alessandro De Laurenzis <just22@atlantide.t28.net>
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# MIT (abc, MiniSat, xSAT), BSD (bzlib, CUDD, satoko), zlib
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PERMIT_PACKAGE_CDROM = Yes
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WANTLIB += ${COMPILER_LIBCXX} c curses m readline
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MODULES = devel/cmake
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USE_GMAKE = Yes
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NO_TEST = Yes
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pre-configure:
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@ln -s `which ${MAKE_PROGRAM}` ${WRKDIR}/bin/make
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do-install:
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${INSTALL_PROGRAM} ${WRKBUILD}/abc ${PREFIX}/bin
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.include <bsd.port.mk>
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